DE3671812D1 - Verfahren zum einebnen der oberflaeche einer halbleitervorrichtung, die siliziumnitrid als isolierendes material verwendet. - Google Patents

Verfahren zum einebnen der oberflaeche einer halbleitervorrichtung, die siliziumnitrid als isolierendes material verwendet.

Info

Publication number
DE3671812D1
DE3671812D1 DE8686201608T DE3671812T DE3671812D1 DE 3671812 D1 DE3671812 D1 DE 3671812D1 DE 8686201608 T DE8686201608 T DE 8686201608T DE 3671812 T DE3671812 T DE 3671812T DE 3671812 D1 DE3671812 D1 DE 3671812D1
Authority
DE
Germany
Prior art keywords
leveling
semiconductor device
insulating material
silicon nitride
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686201608T
Other languages
English (en)
Inventor
Raymond Fabien
Jean-Michel Decrouen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3671812D1 publication Critical patent/DE3671812D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8686201608T 1985-09-20 1986-09-17 Verfahren zum einebnen der oberflaeche einer halbleitervorrichtung, die siliziumnitrid als isolierendes material verwendet. Expired - Lifetime DE3671812D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8513987A FR2587838B1 (fr) 1985-09-20 1985-09-20 Procede pour aplanir la surface d'un dispositif semi-conducteur utilisant du nitrure de silicium comme materiau isolant

Publications (1)

Publication Number Publication Date
DE3671812D1 true DE3671812D1 (de) 1990-07-12

Family

ID=9323109

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686201608T Expired - Lifetime DE3671812D1 (de) 1985-09-20 1986-09-17 Verfahren zum einebnen der oberflaeche einer halbleitervorrichtung, die siliziumnitrid als isolierendes material verwendet.

Country Status (6)

Country Link
US (1) US4692204A (de)
EP (1) EP0216425B1 (de)
JP (1) JPH0797578B2 (de)
CA (1) CA1243134A (de)
DE (1) DE3671812D1 (de)
FR (1) FR2587838B1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
EP0244848A1 (de) * 1986-05-07 1987-11-11 Siemens Aktiengesellschaft Verfahren zum Planarisieren von anorganischen, als Zwischenschichten bei Mehrlagenmetallisierung verwendbaren Isolationsschichten
DE3879321T2 (de) * 1987-08-14 1993-09-16 Fairchild Semiconductor Bestimmung des aetzungsendpunktes.
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection
DE3801976A1 (de) * 1988-01-23 1989-08-03 Telefunken Electronic Gmbh Verfahren zum planarisieren von halbleiteroberflaechen
FR2627902B1 (fr) * 1988-02-26 1990-06-22 Philips Nv Procede pour aplanir la surface d'un dispositif semiconducteur
DE68922474T2 (de) * 1988-12-09 1996-01-11 Philips Electronics Nv Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten.
ATE115770T1 (de) * 1989-09-08 1994-12-15 Siemens Ag Verfahren zur globalen planarisierung von oberflächen für integrierte halbleiterschaltungen.
US4986876A (en) * 1990-05-07 1991-01-22 The United States Of America As Represented By The Secretary Of The Army Method of smoothing patterned transparent electrode stripes in thin film electroluminescent display panel manufacture
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157233A (en) * 1979-05-28 1980-12-06 Hitachi Ltd Method and apparatus for monitoring etching
JPS5750436A (en) * 1980-09-12 1982-03-24 Fujitsu Ltd Manufacture of semiconductor device
DE3164742D1 (en) * 1980-09-22 1984-08-16 Tokyo Shibaura Electric Co Method of smoothing an insulating layer formed on a semiconductor body
US4457820A (en) * 1981-12-24 1984-07-03 International Business Machines Corporation Two step plasma etching
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
JPS59169151A (ja) * 1983-03-17 1984-09-25 Toshiba Corp 半導体装置の製造方法
JPS60100451A (ja) * 1983-11-07 1985-06-04 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
US4515652A (en) * 1984-03-20 1985-05-07 Harris Corporation Plasma sculpturing with a non-planar sacrificial layer
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits

Also Published As

Publication number Publication date
JPH0797578B2 (ja) 1995-10-18
FR2587838B1 (fr) 1987-11-27
EP0216425B1 (de) 1990-06-06
JPS6267825A (ja) 1987-03-27
CA1243134A (en) 1988-10-11
EP0216425A3 (en) 1987-08-05
FR2587838A1 (fr) 1987-03-27
US4692204A (en) 1987-09-08
EP0216425A2 (de) 1987-04-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee