CA1250667A
(en)
*
|
1985-04-15 |
1989-02-28 |
Larry D. Larsen |
Branch control in a three phase pipelined signal processor
|
US4777587A
(en)
|
1985-08-30 |
1988-10-11 |
Advanced Micro Devices, Inc. |
System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
|
US5440704A
(en)
*
|
1986-08-26 |
1995-08-08 |
Mitsubishi Denki Kabushiki Kaisha |
Data processor having branch predicting function
|
US4942520A
(en)
*
|
1987-07-31 |
1990-07-17 |
Prime Computer, Inc. |
Method and apparatus for indexing, accessing and updating a memory
|
JPH0760387B2
(ja)
*
|
1987-11-12 |
1995-06-28 |
松下電器産業株式会社 |
情報処理装置
|
JPH0766326B2
(ja)
*
|
1987-11-12 |
1995-07-19 |
松下電器産業株式会社 |
情報処理装置
|
US5247628A
(en)
*
|
1987-11-30 |
1993-09-21 |
International Business Machines Corporation |
Parallel processor instruction dispatch apparatus with interrupt handler
|
JP2723238B2
(ja)
*
|
1988-01-18 |
1998-03-09 |
株式会社東芝 |
情報処理装置
|
JPH0769808B2
(ja)
*
|
1988-02-23 |
1995-07-31 |
三菱電機株式会社 |
データ処理装置
|
JPH0769817B2
(ja)
*
|
1988-02-29 |
1995-07-31 |
日本電気株式会社 |
条件ジャンプ実行制御方式
|
US4890221A
(en)
*
|
1988-04-01 |
1989-12-26 |
Digital Equipment Corporation |
Apparatus and method for reconstructing a microstack
|
GB8815042D0
(en)
*
|
1988-06-24 |
1988-08-03 |
Int Computers Ltd |
Data processing apparatus
|
US5136696A
(en)
*
|
1988-06-27 |
1992-08-04 |
Prime Computer, Inc. |
High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
|
US5159680A
(en)
*
|
1988-07-28 |
1992-10-27 |
Sun Microsystems, Inc. |
Risc processing unit which selectively isolates register windows by indicating usage of adjacent register windows in status register
|
US5101341A
(en)
*
|
1988-08-25 |
1992-03-31 |
Edgcore Technology, Inc. |
Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
|
US5155818A
(en)
*
|
1988-09-28 |
1992-10-13 |
Data General Corporation |
Unconditional wide branch instruction acceleration
|
EP0365188B1
(de)
*
|
1988-10-18 |
1996-09-18 |
Hewlett-Packard Company |
Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor
|
EP0378415A3
(de)
*
|
1989-01-13 |
1991-09-25 |
International Business Machines Corporation |
Verteilungsmechanismus für mehrere Befehle
|
JPH02212936A
(ja)
*
|
1989-02-14 |
1990-08-24 |
Matsushita Electron Corp |
パイプライン構造を有する半導体装置
|
US5072364A
(en)
*
|
1989-05-24 |
1991-12-10 |
Tandem Computers Incorporated |
Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
|
JPH0795271B2
(ja)
*
|
1989-06-20 |
1995-10-11 |
富士通株式会社 |
分岐命令実行装置
|
US5440749A
(en)
*
|
1989-08-03 |
1995-08-08 |
Nanotronics Corporation |
High performance, low cost microprocessor architecture
|
US5210841A
(en)
*
|
1990-01-30 |
1993-05-11 |
Advanced Micro Devices, Inc. |
External memory accessing system
|
EP0442116A3
(en)
*
|
1990-02-13 |
1993-03-03 |
Hewlett-Packard Company |
Pipeline method and apparatus
|
US5226130A
(en)
*
|
1990-02-26 |
1993-07-06 |
Nexgen Microsystems |
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
|
US5230068A
(en)
*
|
1990-02-26 |
1993-07-20 |
Nexgen Microsystems |
Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
|
US5163140A
(en)
*
|
1990-02-26 |
1992-11-10 |
Nexgen Microsystems |
Two-level branch prediction cache
|
EP0450658B1
(de)
*
|
1990-04-06 |
2001-08-01 |
Nec Corporation |
Parallelfliessband-Befehlsverarbeitungssystem für sehr lange Befehlswörter
|
JPH0437927A
(ja)
*
|
1990-06-01 |
1992-02-07 |
Sony Corp |
プロセッサの処理方法
|
CA2045791A1
(en)
*
|
1990-06-29 |
1991-12-30 |
Richard Lee Sites |
Branch performance in high speed processor
|
WO1992006426A1
(en)
*
|
1990-10-09 |
1992-04-16 |
Nexgen Microsystems |
Method and apparatus for parallel decoding of instructions with branch prediction look-up
|
US5454090A
(en)
*
|
1990-10-12 |
1995-09-26 |
Siemens Aktiengesellschaft |
Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units
|
EP0488819B1
(de)
*
|
1990-11-30 |
1999-01-13 |
Kabushiki Kaisha Toshiba |
Ausführungsvorrichtung für bedingte Verzweigungsbefehle
|
US5265213A
(en)
*
|
1990-12-10 |
1993-11-23 |
Intel Corporation |
Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
|
US5454089A
(en)
*
|
1991-04-17 |
1995-09-26 |
Intel Corporation |
Branch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decoding
|
US5450585A
(en)
*
|
1991-05-15 |
1995-09-12 |
International Business Machines Corporation |
Compiler with delayed conditional branching
|
US5434986A
(en)
*
|
1992-01-09 |
1995-07-18 |
Unisys Corporation |
Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
|
JP2761688B2
(ja)
*
|
1992-02-07 |
1998-06-04 |
三菱電機株式会社 |
データ処理装置
|
US5442756A
(en)
*
|
1992-07-31 |
1995-08-15 |
Intel Corporation |
Branch prediction and resolution apparatus for a superscalar computer processor
|
US5692167A
(en)
*
|
1992-07-31 |
1997-11-25 |
Intel Corporation |
Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
|
US5410660A
(en)
*
|
1992-12-24 |
1995-04-25 |
Motorola, Inc. |
System and method for executing branch on bit set/clear instructions using microprogramming flow
|
US5634025A
(en)
*
|
1993-12-09 |
1997-05-27 |
International Business Machines Corporation |
Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units
|
US5604909A
(en)
|
1993-12-15 |
1997-02-18 |
Silicon Graphics Computer Systems, Inc. |
Apparatus for processing instructions in a computing system
|
US5539888A
(en)
*
|
1993-12-23 |
1996-07-23 |
Unisys Corporation |
System and method for processing external conditional branch instructions
|
US5706459A
(en)
*
|
1994-01-06 |
1998-01-06 |
Fujitsu Limited |
Processor having a variable number of stages in a pipeline
|
GB9412487D0
(en)
*
|
1994-06-22 |
1994-08-10 |
Inmos Ltd |
A computer system for executing branch instructions
|
DE69425377T2
(de)
*
|
1994-11-29 |
2001-02-15 |
International Business Machines Corp., Armonk |
Einzel-Zyklus-Prozessor zur Echtzeitsverarbeitung
|
JPH08212075A
(ja)
*
|
1995-01-31 |
1996-08-20 |
Nec Corp |
情報処理装置
|
US6003127A
(en)
|
1995-10-04 |
1999-12-14 |
Nippondenso Co., Ltd. |
Pipeline processing apparatus for reducing delays in the performance of processing operations
|
US5905881A
(en)
*
|
1995-11-30 |
1999-05-18 |
Unisys Corporation |
Delayed state writes for an instruction processor
|
US5867699A
(en)
*
|
1996-07-25 |
1999-02-02 |
Unisys Corporation |
Instruction flow control for an instruction processor
|
WO1998008160A1
(en)
*
|
1996-08-20 |
1998-02-26 |
Idea Corporation |
A method for identifying hard-to-predict branches to enhance processor performance
|
US5964869A
(en)
*
|
1997-06-19 |
1999-10-12 |
Sun Microsystems, Inc. |
Instruction fetch mechanism with simultaneous prediction of control-flow instructions
|
US5935238A
(en)
*
|
1997-06-19 |
1999-08-10 |
Sun Microsystems, Inc. |
Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
|
JPH1165840A
(ja)
*
|
1997-08-11 |
1999-03-09 |
Sony Corp |
演算処理装置およびその方法
|
US6112299A
(en)
*
|
1997-12-31 |
2000-08-29 |
International Business Machines Corporation |
Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching
|
US6243805B1
(en)
*
|
1998-08-11 |
2001-06-05 |
Advanced Micro Devices, Inc. |
Programming paradigm and microprocessor architecture for exact branch targeting
|
US6289442B1
(en)
|
1998-10-05 |
2001-09-11 |
Advanced Micro Devices, Inc. |
Circuit and method for tagging and invalidating speculatively executed instructions
|
US7191309B1
(en)
|
1999-09-01 |
2007-03-13 |
Intel Corporation |
Double shift instruction for micro engine used in multithreaded parallel processor architecture
|
WO2001016702A1
(en)
|
1999-09-01 |
2001-03-08 |
Intel Corporation |
Register set used in multithreaded parallel processor architecture
|
US7421572B1
(en)
*
|
1999-09-01 |
2008-09-02 |
Intel Corporation |
Branch instruction for processor with branching dependent on a specified bit in a register
|
WO2001046827A1
(en)
*
|
1999-12-22 |
2001-06-28 |
Ubicom, Inc. |
System and method for instruction level multithreading in an embedded processor using zero-time context switching
|
US7120783B2
(en)
|
1999-12-22 |
2006-10-10 |
Ubicom, Inc. |
System and method for reading and writing a thread state in a multithreaded central processing unit
|
US7308686B1
(en)
|
1999-12-22 |
2007-12-11 |
Ubicom Inc. |
Software input/output using hard real time threads
|
US7047396B1
(en)
|
2000-06-22 |
2006-05-16 |
Ubicom, Inc. |
Fixed length memory to memory arithmetic and architecture for a communications embedded processor system
|
US7010612B1
(en)
|
2000-06-22 |
2006-03-07 |
Ubicom, Inc. |
Universal serializer/deserializer
|
US7681018B2
(en)
*
|
2000-08-31 |
2010-03-16 |
Intel Corporation |
Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
|
US20020053017A1
(en)
*
|
2000-09-01 |
2002-05-02 |
Adiletta Matthew J. |
Register instructions for a multithreaded processor
|
US7020871B2
(en)
*
|
2000-12-21 |
2006-03-28 |
Intel Corporation |
Breakpoint method for parallel hardware threads in multithreaded processor
|
US7216204B2
(en)
|
2001-08-27 |
2007-05-08 |
Intel Corporation |
Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
|
US7487505B2
(en)
|
2001-08-27 |
2009-02-03 |
Intel Corporation |
Multithreaded microprocessor with register allocation based on number of active threads
|
US7225281B2
(en)
|
2001-08-27 |
2007-05-29 |
Intel Corporation |
Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
|
US6868476B2
(en)
|
2001-08-27 |
2005-03-15 |
Intel Corporation |
Software controlled content addressable memory in a general purpose execution datapath
|
US7610451B2
(en)
|
2002-01-25 |
2009-10-27 |
Intel Corporation |
Data transfer mechanism using unidirectional pull bus and push bus
|
US7437724B2
(en)
*
|
2002-04-03 |
2008-10-14 |
Intel Corporation |
Registers for data transfers
|
US7337275B2
(en)
|
2002-08-13 |
2008-02-26 |
Intel Corporation |
Free list and ring data structure management
|
US6941438B2
(en)
|
2003-01-10 |
2005-09-06 |
Intel Corporation |
Memory interleaving
|
US7822950B1
(en)
|
2003-01-22 |
2010-10-26 |
Ubicom, Inc. |
Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls
|
US7765388B2
(en)
*
|
2003-09-17 |
2010-07-27 |
Broadcom Corporation |
Interrupt verification support mechanism
|
US7278014B2
(en)
*
|
2004-12-02 |
2007-10-02 |
International Business Machines Corporation |
System and method for simulating hardware interrupts
|
US7478228B2
(en)
*
|
2006-08-31 |
2009-01-13 |
Qualcomm Incorporated |
Apparatus for generating return address predictions for implicit and explicit subroutine calls
|
JP2008165589A
(ja)
*
|
2006-12-28 |
2008-07-17 |
Fujitsu Ltd |
情報処理装置
|
CN102117198B
(zh)
*
|
2009-12-31 |
2015-07-15 |
上海芯豪微电子有限公司 |
一种分支处理方法
|
US9753691B2
(en)
|
2013-03-15 |
2017-09-05 |
Intel Corporation |
Method for a stage optimized high speed adder
|
US11003459B2
(en)
|
2013-03-15 |
2021-05-11 |
Intel Corporation |
Method for implementing a line speed interconnect structure
|
US9817666B2
(en)
|
2013-03-15 |
2017-11-14 |
Intel Corporation |
Method for a delayed branch implementation by using a front end track table
|
KR101763731B1
(ko)
|
2013-03-15 |
2017-08-01 |
인텔 코포레이션 |
회선 속도 상호 연결 구조를 구현하는 방법
|
US20170277539A1
(en)
*
|
2016-03-24 |
2017-09-28 |
Imagination Technologies Limited |
Exception handling in processor using branch delay slot instruction set architecture
|