JPS57113146A - Instruction refetch system - Google Patents

Abstract

PURPOSE:To improve processing efficiency by preventing unnecessary instructions from being refetched, by checking the overlap between an instruction prefetch area and a data write area by using variable arithmetic data length stored by a general instruction. CONSTITUTION:When arithmetic data is to be stored in a prefetched-instruction area, an advanced control type high-speed data processor discriminates whether a prefetched instruction needs be refetched or not. In this case, arithmetic data length l stored by a general instruction, prefetched-instruction length Li, the ending address Mi of the prefetched instruction, and the starting address MS of the arithmetic data to be stored are held in registers respectively; the variable values l and Li are processed by addition 9 and an adder 5 finds Mi-Ms-(l+ Li) through complement circuits 4 and 10. Then, its plus or minus sign is detected and when it is plus, the decision 6 is made that the refetching of the instruction is unnecessary. Thus, the variable value (l) is used to check the overlap between the instruction prefetch area and data write area, so the unnecessary instruction refetching is prevented to improve processing efficiency.