DE3618136C2 - - Google Patents

Info

Publication number
DE3618136C2
DE3618136C2 DE3618136A DE3618136A DE3618136C2 DE 3618136 C2 DE3618136 C2 DE 3618136C2 DE 3618136 A DE3618136 A DE 3618136A DE 3618136 A DE3618136 A DE 3618136A DE 3618136 C2 DE3618136 C2 DE 3618136C2
Authority
DE
Germany
Prior art keywords
address
signal
data
memory cell
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3618136A
Other languages
German (de)
English (en)
Other versions
DE3618136A1 (de
Inventor
Tatsuo Itami Hyogo Jp Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3618136A1 publication Critical patent/DE3618136A1/de
Application granted granted Critical
Publication of DE3618136C2 publication Critical patent/DE3618136C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
DE19863618136 1985-06-21 1986-05-30 Abwechselnd adressierte halbleiterspeichergruppe Granted DE3618136A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60136539A JPS61294562A (ja) 1985-06-21 1985-06-21 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3618136A1 DE3618136A1 (de) 1987-01-02
DE3618136C2 true DE3618136C2 (OSRAM) 1992-02-13

Family

ID=15177554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863618136 Granted DE3618136A1 (de) 1985-06-21 1986-05-30 Abwechselnd adressierte halbleiterspeichergruppe

Country Status (3)

Country Link
US (1) US4763302A (OSRAM)
JP (1) JPS61294562A (OSRAM)
DE (1) DE3618136A1 (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4321473A1 (de) * 1992-06-26 1994-03-10 Mitsubishi Electric Corp FIFO-Speichereinrichtung

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3884492T2 (de) * 1987-07-15 1994-02-17 Hitachi Ltd Integrierte Halbleiterschaltungsanordnung.
US5257234A (en) * 1987-07-15 1993-10-26 Hitachi, Ltd. Semiconductor integrated circuit device
US5021689A (en) * 1989-01-19 1991-06-04 National Semiconductor Corp. Multiple page programmable logic architecture
US4942319A (en) * 1989-01-19 1990-07-17 National Semiconductor Corp. Multiple page programmable logic architecture
US5307469A (en) * 1989-05-05 1994-04-26 Wang Laboratories, Inc. Multiple mode memory module
US6564308B2 (en) 1989-05-05 2003-05-13 Samsung Electronics Co. Ltd. Multiple mode memory module
US5261073A (en) * 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US5247655A (en) * 1989-11-07 1993-09-21 Chips And Technologies, Inc. Sleep mode refresh apparatus
US4985871A (en) * 1989-11-13 1991-01-15 Chips And Technologies, Inc. Memory controller for using reserved dram addresses for expanded memory space
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US4999815A (en) * 1990-02-13 1991-03-12 International Business Machines Corporation Low power addressing systems
JP2900523B2 (ja) * 1990-05-31 1999-06-02 日本電気株式会社 不揮発性半導体メモリ装置の書込回路
US5526503A (en) * 1993-10-06 1996-06-11 Ast Research, Inc. Virtual addressing buffer circuit
US5532947A (en) * 1995-01-25 1996-07-02 International Business Machines Corporation Combined decoder/adder circuit which provides improved access speed to a cache
US6016560A (en) 1995-06-14 2000-01-18 Hitachi, Ltd. Semiconductor memory, memory device, and memory card
US6154825A (en) * 1997-03-07 2000-11-28 Intel Corporation Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations
KR100281900B1 (ko) * 1998-09-08 2001-02-15 윤종용 개선된 웨이퍼 번인 테스트 스킴을 갖는 반도체 메모리장치
TW516118B (en) * 2001-09-11 2003-01-01 Leadtek Research Inc Decoding conversion device and method capable of supporting multiple memory chips and their application system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800289A (en) * 1972-05-15 1974-03-26 Goodyear Aerospace Corp Multi-dimensional access solid state memory
CH613540A5 (OSRAM) * 1975-02-26 1979-09-28 Siemens Ag
DE2942741A1 (de) * 1979-10-23 1981-05-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Anordnung fuer einen speicher mit wahlfreiem zugriff
US4494222A (en) * 1980-03-28 1985-01-15 Texas Instruments Incorporated Processor system using on-chip refresh address generator for dynamic memory
JPS573289A (en) * 1980-06-04 1982-01-08 Hitachi Ltd Semiconductor storing circuit device
JPS60200287A (ja) * 1984-03-24 1985-10-09 株式会社東芝 記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4321473A1 (de) * 1992-06-26 1994-03-10 Mitsubishi Electric Corp FIFO-Speichereinrichtung
DE4321473C2 (de) * 1992-06-26 1998-04-09 Mitsubishi Electric Corp FIFO-Speichereinrichtung

Also Published As

Publication number Publication date
DE3618136A1 (de) 1987-01-02
JPS61294562A (ja) 1986-12-25
US4763302A (en) 1988-08-09

Similar Documents

Publication Publication Date Title
DE3618136C2 (OSRAM)
DE2753063C3 (OSRAM)
DE3638632C2 (OSRAM)
DE2803989C2 (de) Digitaldatenspeicher mit wahlfreiem Zugriff
DE3886114T2 (de) Halbleiterspeichergerät mit redundanter Speicherzellenmatrix.
DE69024851T2 (de) Halbleiterspeicheranordnung
DE2364785C3 (de) Integrierter Halbleiterspeicher mit nach guten und defekten Speicherzellen sortierten Speicherzellen
DE3686994T2 (de) Halbleiterspeicher.
EP0908893B1 (de) Speicherarchitektur mit Mehrebenenhierarchie
DE3788747T2 (de) Halbleiterspeicher.
DE68924639T2 (de) Matrixspeicher, der Standardblöcke, Standard-Unterblöcke, einen redundanten Block und redundante Unterblöcke beinhaltet, und integrierter Kreis, der eine Vielzahl solcher Matrixspeicher beinhaltet.
DE2646163B2 (de) Schaltungsanordnung zum Ersetzen fehlerhafter Informationen in Speicherplätzen eines nicht veränderbaren Speichers
DE19614443A1 (de) Inhalts-adressierbarer Speicher
DE69020384T2 (de) Integrierte Halbleiterspeicherschaltung mit Möglichkeit zum Maskieren des Schreibens im Speicher.
DE3716518A1 (de) Halbleiterspeichervorrichtung
DE102006062399A1 (de) Halbleiterspeicherbauelement mit mehreren Speicherbereichen, Zugriffsverfahren und Testverfahren
DE3032630A1 (de) Halbleiterspeicher aus speicherbausteinen mit redundanten speicherbereichen
DE2926322C2 (de) Speicher-Subsystem
DE2758829C2 (de) Datenverarbeitungsanlage mit mehreren Prozessoren
DE19723432B4 (de) Halbleiterspeicher-Bauelement mit Bänken
DE69326236T2 (de) Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit
DE69125876T2 (de) Kennzeichenschaltung für nichtflüchtige Speicheranordnung
DE3200880A1 (de) Halbleiterspeicher
DE2703559A1 (de) Rechnersystem
DE2900586A1 (de) Anordnung zum decodieren von codewoertern variabler laenge

Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)