DE3584594D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3584594D1
DE3584594D1 DE8585305659T DE3584594T DE3584594D1 DE 3584594 D1 DE3584594 D1 DE 3584594D1 DE 8585305659 T DE8585305659 T DE 8585305659T DE 3584594 T DE3584594 T DE 3584594T DE 3584594 D1 DE3584594 D1 DE 3584594D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585305659T
Other languages
English (en)
Inventor
Yoshinori Okajima
Tomoharu Awaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3584594D1 publication Critical patent/DE3584594D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
DE8585305659T 1984-08-10 1985-08-09 Halbleiterspeicheranordnung. Expired - Fee Related DE3584594D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59167395A JPS6145491A (ja) 1984-08-10 1984-08-10 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3584594D1 true DE3584594D1 (de) 1991-12-12

Family

ID=15848901

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585305659T Expired - Fee Related DE3584594D1 (de) 1984-08-10 1985-08-09 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4740918A (de)
EP (1) EP0171292B1 (de)
JP (1) JPS6145491A (de)
KR (1) KR900004633B1 (de)
DE (1) DE3584594D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165696A (ja) * 1986-12-27 1988-07-08 日本鋼管株式会社 非開削管推進工法における掘削体の方向修正用機構
JPS63266692A (ja) * 1987-04-24 1988-11-02 Hitachi Ltd 半導体記憶装置
JPS6474823A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Emitter follower circuit
US4984211A (en) * 1988-02-16 1991-01-08 Texas Instruments Incorporated Battery backup bus scheme for an ECL BiCMOS SRAM
US5267201A (en) * 1990-04-06 1993-11-30 Mosaid, Inc. High voltage boosted word line supply charge pump regulator for DRAM
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US6198670B1 (en) 1999-06-22 2001-03-06 Micron Technology, Inc. Bias generator for a four transistor load less memory cell
US8929128B2 (en) * 2012-05-17 2015-01-06 Semiconductor Energy Laboratory Co., Ltd. Storage device and writing method of the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3365707A (en) * 1967-06-23 1968-01-23 Rca Corp Lsi array and standard cells
US3898630A (en) * 1973-10-11 1975-08-05 Ibm High voltage integrated driver circuit
GB1595451A (en) * 1976-11-26 1981-08-12 Solartron Electronic Group Multi function patch pin circuit
DE2855744C3 (de) * 1978-12-22 1982-02-18 Siemens AG, 1000 Berlin und 8000 München MOS-integrierte Schaltungsanordnung zur Unterdrückung von in Wortleitungstreibern von Halbleiterspeicher fließenden Ruheströmen
JPS5843836B2 (ja) * 1979-12-21 1983-09-29 富士通株式会社 デコ−ダ回路
JPS5884445A (ja) * 1981-11-16 1983-05-20 Hitachi Ltd 大規模集積回路
US4627034A (en) * 1984-11-09 1986-12-02 Fairchild Camera And Instrument Corporation Memory cell power scavenging apparatus and method

Also Published As

Publication number Publication date
KR900004633B1 (ko) 1990-06-30
JPS6145491A (ja) 1986-03-05
EP0171292B1 (de) 1991-11-06
JPH0467720B2 (de) 1992-10-29
KR870002584A (ko) 1987-03-31
EP0171292A3 (en) 1989-01-25
US4740918A (en) 1988-04-26
EP0171292A2 (de) 1986-02-12

Similar Documents

Publication Publication Date Title
DE3585711D1 (de) Halbleiterspeicheranordnung.
DE3583091D1 (de) Halbleiterspeicheranordnung.
DE3577944D1 (de) Halbleiterspeicheranordnung.
DE3686994D1 (de) Halbleiterspeicher.
DE3687322D1 (de) Halbleiterspeicheranordnung.
DE3582376D1 (de) Halbleiterspeicheranordnung.
DE3586377T2 (de) Halbleiterspeicheranordnung.
DE3576236D1 (de) Halbleiterspeicheranordnung.
DE3577367D1 (de) Halbleiterspeicheranordnung.
DE3680562D1 (de) Halbleiterspeicheranordnung.
DE3675445D1 (de) Halbleiterspeicheranordnung.
DE3580993D1 (de) Halbleiterspeicheranordnung.
DE3586556T2 (de) Halbleiterspeicheranordnung.
DE3575225D1 (de) Halbleiterspeicheranordnung.
DE3576754D1 (de) Halbleiterspeicheranordnung.
DE3586675T2 (de) Halbleiterspeicheranordnung.
DE3582960D1 (de) Halbleiterspeicheranordnung.
DE3580454D1 (de) Halbleiterspeicheranordnung.
DE3578254D1 (de) Halbleiterspeicheranordnung.
DE3586736D1 (de) Halbleiterspeicher.
DE3687284D1 (de) Halbleiterspeicheranordnung.
DE3682346D1 (de) Halbleiterspeicheranordnung.
DE3683783D1 (de) Halbleiterspeicheranordnung.
DE3581888D1 (de) Halbleiterspeicheranordnung.
DE3685889D1 (de) Halbleiterspeicheranordnung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee