DE3581888D1 - Halbleiterspeicheranordnung. - Google Patents
Halbleiterspeicheranordnung.Info
- Publication number
- DE3581888D1 DE3581888D1 DE8585307971T DE3581888T DE3581888D1 DE 3581888 D1 DE3581888 D1 DE 3581888D1 DE 8585307971 T DE8585307971 T DE 8585307971T DE 3581888 T DE3581888 T DE 3581888T DE 3581888 D1 DE3581888 D1 DE 3581888D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory arrangement
- arrangement
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59232733A JPS61110396A (ja) | 1984-11-05 | 1984-11-05 | 半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3581888D1 true DE3581888D1 (de) | 1991-04-04 |
Family
ID=16943925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585307971T Expired - Fee Related DE3581888D1 (de) | 1984-11-05 | 1985-11-04 | Halbleiterspeicheranordnung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4970693A (de) |
EP (1) | EP0181177B1 (de) |
JP (1) | JPS61110396A (de) |
KR (1) | KR900007999B1 (de) |
DE (1) | DE3581888D1 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0197014A (ja) * | 1987-10-09 | 1989-04-14 | Toshiba Corp | 半導体集積回路 |
JP2777136B2 (ja) * | 1988-03-08 | 1998-07-16 | 株式会社東芝 | 半導体集積回路の誤動作防止回路 |
JPH01238217A (ja) * | 1988-03-18 | 1989-09-22 | Toshiba Corp | 半導体集積回路の誤動作防止回路 |
US5206833A (en) * | 1988-09-12 | 1993-04-27 | Acer Incorporated | Pipelined dual port RAM |
JPH0756749B2 (ja) * | 1989-09-29 | 1995-06-14 | 株式会社東芝 | 機能選択回路 |
TW198135B (de) * | 1990-11-20 | 1993-01-11 | Oki Electric Ind Co Ltd | |
US5485430A (en) * | 1992-12-22 | 1996-01-16 | Sgs-Thomson Microelectronics, Inc. | Multiple clocked dynamic sense amplifier |
JP2605576B2 (ja) * | 1993-04-02 | 1997-04-30 | 日本電気株式会社 | 同期型半導体メモリ |
KR940026946A (ko) * | 1993-05-12 | 1994-12-10 | 김광호 | 데이타출력 확장방법과 이를 통한 신뢰성있는 유효데이타의 출력이 이루어지는 반도체집적회로 |
JPH0715312A (ja) * | 1993-06-15 | 1995-01-17 | Fujitsu Ltd | 半導体記憶装置 |
JP2697634B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
US5550783A (en) * | 1995-04-19 | 1996-08-27 | Alliance Semiconductor Corporation | Phase shift correction circuit for monolithic random access memory |
US8193599B2 (en) * | 2009-09-02 | 2012-06-05 | Himax Semiconductor, Inc. | Fabricating method and structure of a wafer level module |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4165541A (en) * | 1977-12-12 | 1979-08-21 | Fairchild Camera And Instrument Corporation | Serial-parallel-serial charge-coupled device memory having interlacing and ripple clocking of the parallel shift registers |
US4337525A (en) * | 1979-04-17 | 1982-06-29 | Nippon Electric Co., Ltd. | Asynchronous circuit responsive to changes in logic level |
JPS5835783A (ja) * | 1981-08-24 | 1983-03-02 | Fujitsu Ltd | 半導体メモリ |
US4585955B1 (en) * | 1982-12-15 | 2000-11-21 | Tokyo Shibaura Electric Co | Internally regulated power voltage circuit for mis semiconductor integrated circuit |
JPS6052112A (ja) * | 1983-08-31 | 1985-03-25 | Toshiba Corp | 論理回路 |
US4638182A (en) * | 1984-07-11 | 1987-01-20 | Texas Instruments Incorporated | High-level CMOS driver circuit |
-
1984
- 1984-11-05 JP JP59232733A patent/JPS61110396A/ja active Granted
-
1985
- 1985-11-04 DE DE8585307971T patent/DE3581888D1/de not_active Expired - Fee Related
- 1985-11-04 EP EP85307971A patent/EP0181177B1/de not_active Expired - Lifetime
- 1985-11-05 KR KR1019850008230A patent/KR900007999B1/ko not_active IP Right Cessation
-
1990
- 1990-02-23 US US07/484,474 patent/US4970693A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR900007999B1 (ko) | 1990-10-23 |
EP0181177A3 (en) | 1988-03-02 |
EP0181177A2 (de) | 1986-05-14 |
JPH0439158B2 (de) | 1992-06-26 |
US4970693A (en) | 1990-11-13 |
EP0181177B1 (de) | 1991-02-27 |
JPS61110396A (ja) | 1986-05-28 |
KR860004380A (ko) | 1986-06-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |