DE3577776D1 - Verfahren zur herstellung submikronischer graeben, z.b. in halbleitermaterial und nach diesem verfahren hergestellte anordnungen. - Google Patents

Verfahren zur herstellung submikronischer graeben, z.b. in halbleitermaterial und nach diesem verfahren hergestellte anordnungen.

Info

Publication number
DE3577776D1
DE3577776D1 DE8585201462T DE3577776T DE3577776D1 DE 3577776 D1 DE3577776 D1 DE 3577776D1 DE 8585201462 T DE8585201462 T DE 8585201462T DE 3577776 T DE3577776 T DE 3577776T DE 3577776 D1 DE3577776 D1 DE 3577776D1
Authority
DE
Germany
Prior art keywords
submicronic
trenches
producing
semiconductor material
arrangements produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585201462T
Other languages
English (en)
Inventor
Henricus Godefridus Rafae Maas
Johannes Arnoldus Appels
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3577776D1 publication Critical patent/DE3577776D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
DE8585201462T 1984-09-18 1985-09-13 Verfahren zur herstellung submikronischer graeben, z.b. in halbleitermaterial und nach diesem verfahren hergestellte anordnungen. Expired - Lifetime DE3577776D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8402859A NL8402859A (nl) 1984-09-18 1984-09-18 Werkwijze voor het vervaardigen van submicrongroeven in bijvoorbeeld halfgeleidermateriaal en met deze werkwijze verkregen inrichtingen.
CN85103535A CN85103535B (zh) 1984-09-18 1985-05-06 在材料(例如半导体材料)中加工亚微型槽的方法以及用这种方法制成的器件

Publications (1)

Publication Number Publication Date
DE3577776D1 true DE3577776D1 (de) 1990-06-21

Family

ID=25741633

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585201462T Expired - Lifetime DE3577776D1 (de) 1984-09-18 1985-09-13 Verfahren zur herstellung submikronischer graeben, z.b. in halbleitermaterial und nach diesem verfahren hergestellte anordnungen.

Country Status (6)

Country Link
US (1) US4717689A (de)
EP (1) EP0178000B1 (de)
JP (1) JPS6174342A (de)
CN (1) CN85103535B (de)
DE (1) DE3577776D1 (de)
NL (1) NL8402859A (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924287A (en) * 1985-01-20 1990-05-08 Avner Pdahtzur Personalizable CMOS gate array device and technique
NL190388C (nl) * 1986-02-07 1994-02-01 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een halfgeleiderinrichting en halfgeleiderinrichting.
JPS63193562A (ja) * 1987-02-06 1988-08-10 Toshiba Corp バイポ−ラトランジスタの製造方法
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
US4799990A (en) * 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region
US4847670A (en) * 1987-05-11 1989-07-11 International Business Machines Corporation High performance sidewall emitter transistor
US4916083A (en) * 1987-05-11 1990-04-10 International Business Machines Corporation High performance sidewall emitter transistor
US4814290A (en) * 1987-10-30 1989-03-21 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US5008210A (en) * 1989-02-07 1991-04-16 Hewlett-Packard Company Process of making a bipolar transistor with a trench-isolated emitter
JP2741964B2 (ja) * 1991-04-15 1998-04-22 シャープ株式会社 半導体装置の製造方法
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor
US5245206A (en) * 1992-05-12 1993-09-14 International Business Machines Corporation Capacitors with roughened single crystal plates
US5414283A (en) * 1993-11-19 1995-05-09 Ois Optical Imaging Systems, Inc. TFT with reduced parasitic capacitance
US5389559A (en) * 1993-12-02 1995-02-14 International Business Machines Corporation Method of forming integrated interconnect for very high density DRAMs
KR0157928B1 (ko) * 1995-12-27 1998-12-15 문정환 자체 접합형 아웃-리거 위상반전마스크 제조방법
KR100456698B1 (ko) * 2002-09-04 2004-11-10 삼성전자주식회사 강유전체 메모리 소자의 제조 방법
JP5184476B2 (ja) * 2009-09-17 2013-04-17 東京エレクトロン株式会社 基板液処理方法、基板液処理装置および記憶媒体

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3536547A (en) * 1968-03-25 1970-10-27 Bell Telephone Labor Inc Plasma deposition of oxide coatings on silicon and electron bombardment of portions thereof to be etched selectively
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
JPS52128066A (en) * 1976-04-20 1977-10-27 Matsushita Electronics Corp Manufacture of semiconductor device
CA1129118A (en) * 1978-07-19 1982-08-03 Tetsushi Sakai Semiconductor devices and method of manufacturing the same
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
JPS5893343A (ja) * 1981-11-30 1983-06-03 Toshiba Corp 半導体集積回路の分離領域形成方法
NL8105559A (nl) * 1981-12-10 1983-07-01 Philips Nv Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied.
JPS58153373A (ja) * 1982-03-08 1983-09-12 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPS58175847A (ja) * 1982-04-08 1983-10-15 Toshiba Corp 半導体装置の製造方法
NL8202686A (nl) * 1982-07-05 1984-02-01 Philips Nv Werkwijze ter vervaardiging van een veldeffektinrichting met geisoleerde stuurelektrode, en inrichting vervaardigd volgens de werkwijze.
US4545114A (en) * 1982-09-30 1985-10-08 Fujitsu Limited Method of producing semiconductor device
NL8301262A (nl) * 1983-04-11 1984-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij met behulp van ionenimplantatie patronen worden aangebracht in een laag siliciumnitride.
US4601778A (en) * 1985-02-25 1986-07-22 Motorola, Inc. Maskless etching of polysilicon

Also Published As

Publication number Publication date
US4717689A (en) 1988-01-05
CN85103535A (zh) 1986-11-05
EP0178000B1 (de) 1990-05-16
CN85103535B (zh) 1988-08-10
JPS6174342A (ja) 1986-04-16
EP0178000A3 (en) 1986-04-23
NL8402859A (nl) 1986-04-16
EP0178000A2 (de) 1986-04-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee