DE3577494D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3577494D1
DE3577494D1 DE8585401626T DE3577494T DE3577494D1 DE 3577494 D1 DE3577494 D1 DE 3577494D1 DE 8585401626 T DE8585401626 T DE 8585401626T DE 3577494 T DE3577494 T DE 3577494T DE 3577494 D1 DE3577494 D1 DE 3577494D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585401626T
Other languages
English (en)
Inventor
Fumio Baba
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3577494D1 publication Critical patent/DE3577494D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE8585401626T 1984-08-11 1985-08-09 Halbleiterspeicheranordnung. Expired - Fee Related DE3577494D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59167276A JPS6148192A (ja) 1984-08-11 1984-08-11 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3577494D1 true DE3577494D1 (de) 1990-06-07

Family

ID=15846740

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585401626T Expired - Fee Related DE3577494D1 (de) 1984-08-11 1985-08-09 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4680734A (de)
EP (1) EP0172112B1 (de)
JP (1) JPS6148192A (de)
KR (1) KR900000052B1 (de)
DE (1) DE3577494D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177392A (ja) * 1987-01-19 1988-07-21 Toshiba Corp 半導体記憶装置
US5189639A (en) * 1987-11-26 1993-02-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having bit lines capable of partial operation
JP2680007B2 (ja) * 1987-12-04 1997-11-19 株式会社日立製作所 半導体メモリ
JPH0752577B2 (ja) * 1988-01-07 1995-06-05 株式会社東芝 半導体メモリ
DE3850483T2 (de) * 1987-12-21 1994-10-20 Toshiba Kawasaki Kk Halbleiterspeicher, der fähig zur Verbesserung der Datenwiedereinschreibgeschwindigkeit ist.
US5267210A (en) * 1988-05-18 1993-11-30 Sgs-Thomson Microelectronics, Inc. SRAM with flash clear for selectable I/OS
JPH0770212B2 (ja) * 1988-07-19 1995-07-31 日本電気株式会社 半導体メモリ回路
JPH0283892A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
JP3191550B2 (ja) * 1994-02-15 2001-07-23 松下電器産業株式会社 半導体メモリ装置
GB2321123B (en) * 1997-01-11 2001-01-03 Motorola Ltd Circuit for erasing a memory and a method thereof
KR100459726B1 (ko) * 2002-10-05 2004-12-03 삼성전자주식회사 멀티-비트 프리페치 반도체 장치의 데이터 반전 회로 및데이터 반전 방법
KR102082144B1 (ko) * 2018-06-29 2020-02-27 창원대학교 산학협력단 이이피롬의 데이터버스 회로

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140830A (de) * 1974-10-04 1976-04-06 Nippon Electric Co
JPS5951072B2 (ja) * 1979-02-26 1984-12-12 日本電気株式会社 半導体メモリ装置
JPS6032912B2 (ja) * 1979-09-13 1985-07-31 株式会社東芝 Ｃｍｏｓセンスアンプ回路
JPS58182194A (ja) * 1982-04-20 1983-10-25 Nec Corp ダイナミツクメモリ集積回路
JPS59104791A (ja) * 1982-12-04 1984-06-16 Fujitsu Ltd 半導体記憶装置
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置
JPS60127599A (ja) * 1983-12-14 1985-07-08 Toshiba Corp ダイナミツク型ランダムアクセスメモリ

Also Published As

Publication number Publication date
EP0172112B1 (de) 1990-05-02
KR900000052B1 (ko) 1990-01-18
KR870002585A (ko) 1987-03-31
EP0172112A2 (de) 1986-02-19
JPS6148192A (ja) 1986-03-08
US4680734A (en) 1987-07-14
EP0172112A3 (en) 1988-02-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee