DE3133548A1 - Verfahren zur herstellung von halbleitervorrichtungen - Google Patents

Verfahren zur herstellung von halbleitervorrichtungen

Info

Publication number
DE3133548A1
DE3133548A1 DE19813133548 DE3133548A DE3133548A1 DE 3133548 A1 DE3133548 A1 DE 3133548A1 DE 19813133548 DE19813133548 DE 19813133548 DE 3133548 A DE3133548 A DE 3133548A DE 3133548 A1 DE3133548 A1 DE 3133548A1
Authority
DE
Germany
Prior art keywords
impurity
pattern
film
conductivity type
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19813133548
Other languages
German (de)
English (en)
Other versions
DE3133548C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Yoshitaka Yokahama Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE3133548A1 publication Critical patent/DE3133548A1/de
Application granted granted Critical
Publication of DE3133548C2 publication Critical patent/DE3133548C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE19813133548 1980-08-25 1981-08-25 Verfahren zur herstellung von halbleitervorrichtungen Granted DE3133548A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55116562A JPS5936432B2 (ja) 1980-08-25 1980-08-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3133548A1 true DE3133548A1 (de) 1982-04-15
DE3133548C2 DE3133548C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-19

Family

ID=14690175

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813133548 Granted DE3133548A1 (de) 1980-08-25 1981-08-25 Verfahren zur herstellung von halbleitervorrichtungen

Country Status (3)

Country Link
US (1) US4407059A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5936432B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3133548A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539742A (en) * 1981-06-22 1985-09-10 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
JPS5946065A (ja) * 1982-09-09 1984-03-15 Toshiba Corp 半導体装置の製造方法
JPS5989457A (ja) * 1982-11-15 1984-05-23 Hitachi Ltd 半導体装置の製造方法
US4555842A (en) * 1984-03-19 1985-12-03 At&T Bell Laboratories Method of fabricating VLSI CMOS devices having complementary threshold voltages
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
US4722830A (en) * 1986-05-05 1988-02-02 General Electric Company Automated multiple stream analysis system
US5169795A (en) * 1989-02-28 1992-12-08 Small Power Communication Systems Research Laboratories Co., Ltd. Method of manufacturing step cut type insulated gate SIT having low-resistance electrode
US5219779A (en) * 1989-05-11 1993-06-15 Sharp Kabushiki Kaisha Memory cell for dynamic random access memory
EP0600693A3 (en) * 1992-11-30 1994-11-30 Sgs Thomson Microelectronics Selective trench etching and self-aligning base-emitter structure.
JP3223895B2 (ja) * 1998-12-15 2001-10-29 日本電気株式会社 半導体装置の製造方法
JP2014241367A (ja) * 2013-06-12 2014-12-25 三菱電機株式会社 半導体素子、半導体素子の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2911132A1 (de) * 1978-03-27 1979-10-11 Intel Corp Verfahren zur bildung einer kontaktzone zwischen schichten aus polysilizium
DE2937989A1 (de) * 1978-09-11 1980-04-10 Tokyo Shibaura Electric Co Halbleitervorrichtung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
JPS54161894A (en) * 1978-06-13 1979-12-21 Toshiba Corp Manufacture of semiconductor device
DE3071489D1 (en) * 1979-11-29 1986-04-17 Vlsi Technology Res Ass Method of manufacturing a semiconductor device with a schottky junction
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact
US4317276A (en) * 1980-06-12 1982-03-02 Teletype Corporation Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2911132A1 (de) * 1978-03-27 1979-10-11 Intel Corp Verfahren zur bildung einer kontaktzone zwischen schichten aus polysilizium
DE2937989A1 (de) * 1978-09-11 1980-04-10 Tokyo Shibaura Electric Co Halbleitervorrichtung

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Vol. SC-12, Nr. 2, April 1977, S. 135-138 *
IEEE Journal of Solid-State-Circuits, Vol. SC-11, No. 4, August 1976, S. 491-495 *
IEEE Transactions on Electron Devices, Vol. ED 26, Nr. 4, April 1979, S. 385-389 *
IEEE Transactions on Electron Devices, Vol. ED-27,No. 8, August 1980, S. 1390-1394 *
International Electron Device Meeting Digest Bd. 25, 1979, S. 201-204 *
J. Electrochemical Soc.: Solid-State Science and Technology, April 1977, Vol. 124, No. 4, S. 630-632 *
Jap. J. Appl. Phys., Vol. 17, 1978, No. 2, S. 457-458 *
Journal of the Electrochemical Society: Solid State Science Technology, Vol. 125, Nr. 3, März 1978, S. 471 und 472 *

Also Published As

Publication number Publication date
JPS5740975A (en) 1982-03-06
DE3133548C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-19
US4407059A (en) 1983-10-04
JPS5936432B2 (ja) 1984-09-04

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8128 New person/name/address of the agent

Representative=s name: HENKEL, G., DR.PHIL. FEILER, L., DR.RER.NAT. HAENZ

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee