DE3129487A1 - Element der integrierten injektionslogik - Google Patents

Element der integrierten injektionslogik

Info

Publication number
DE3129487A1
DE3129487A1 DE19813129487 DE3129487A DE3129487A1 DE 3129487 A1 DE3129487 A1 DE 3129487A1 DE 19813129487 DE19813129487 DE 19813129487 DE 3129487 A DE3129487 A DE 3129487A DE 3129487 A1 DE3129487 A1 DE 3129487A1
Authority
DE
Germany
Prior art keywords
polycrystalline
conductivity type
lateral
area
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19813129487
Other languages
German (de)
English (en)
Other versions
DE3129487C2 (enExample
Inventor
Madhukar B. Los Gatos Calif. Vora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of DE3129487A1 publication Critical patent/DE3129487A1/de
Application granted granted Critical
Publication of DE3129487C2 publication Critical patent/DE3129487C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE19813129487 1980-08-04 1981-07-27 Element der integrierten injektionslogik Granted DE3129487A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10642880A 1980-08-04 1980-08-04

Publications (2)

Publication Number Publication Date
DE3129487A1 true DE3129487A1 (de) 1982-06-24
DE3129487C2 DE3129487C2 (enExample) 1987-06-04

Family

ID=22311366

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813129487 Granted DE3129487A1 (de) 1980-08-04 1981-07-27 Element der integrierten injektionslogik

Country Status (4)

Country Link
JP (1) JPS5753973A (enExample)
DE (1) DE3129487A1 (enExample)
GB (1) GB2081508B (enExample)
NL (1) NL8103031A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19529689A1 (de) * 1995-02-07 1996-08-08 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren derselben

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0147249B1 (en) * 1983-09-19 1989-01-18 Fairchild Semiconductor Corporation Method of manufacturing transistor structures having junctions bound by insulating layers, and resulting structures
EP0948046A1 (en) * 1998-03-26 1999-10-06 Texas Instruments Incorporated Merged bipolar and CMOS circuit and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021403A1 (en) * 1979-06-29 1981-01-07 International Business Machines Corporation Self-aligned semiconductor circuits
DE3100839A1 (de) * 1980-02-04 1981-11-19 Fairchild Camera and Instrument Corp., 94042 Mountain View, Calif. Integrierte schaltungsanordnung

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021403A1 (en) * 1979-06-29 1981-01-07 International Business Machines Corporation Self-aligned semiconductor circuits
DE3100839A1 (de) * 1980-02-04 1981-11-19 Fairchild Camera and Instrument Corp., 94042 Mountain View, Calif. Integrierte schaltungsanordnung

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
US-Z.: "IBM TDB", Bd. 22, Nr. 7, Dez. 1979, S. 2786-2788 *
US-Z.: "IBM TDB", Bd. 22, Nr. 7, Dez. 1979, S. 2948-2951 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19529689A1 (de) * 1995-02-07 1996-08-08 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren derselben

Also Published As

Publication number Publication date
NL8103031A (nl) 1982-03-01
GB2081508A (en) 1982-02-17
DE3129487C2 (enExample) 1987-06-04
GB2081508B (en) 1985-04-17
JPS5753973A (enExample) 1982-03-31

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee