GB2081508B - Integrated injection logic cell having selfaligned collector and base reduced base resistance and method of making same - Google Patents

Integrated injection logic cell having selfaligned collector and base reduced base resistance and method of making same

Info

Publication number
GB2081508B
GB2081508B GB8121920A GB8121920A GB2081508B GB 2081508 B GB2081508 B GB 2081508B GB 8121920 A GB8121920 A GB 8121920A GB 8121920 A GB8121920 A GB 8121920A GB 2081508 B GB2081508 B GB 2081508B
Authority
GB
United Kingdom
Prior art keywords
base
selfaligned
collector
making same
logic cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8121920A
Other languages
English (en)
Other versions
GB2081508A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB2081508A publication Critical patent/GB2081508A/en
Application granted granted Critical
Publication of GB2081508B publication Critical patent/GB2081508B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
GB8121920A 1980-08-04 1981-07-16 Integrated injection logic cell having selfaligned collector and base reduced base resistance and method of making same Expired GB2081508B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10642880A 1980-08-04 1980-08-04

Publications (2)

Publication Number Publication Date
GB2081508A GB2081508A (en) 1982-02-17
GB2081508B true GB2081508B (en) 1985-04-17

Family

ID=22311366

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8121920A Expired GB2081508B (en) 1980-08-04 1981-07-16 Integrated injection logic cell having selfaligned collector and base reduced base resistance and method of making same

Country Status (4)

Country Link
JP (1) JPS5753973A (enExample)
DE (1) DE3129487A1 (enExample)
GB (1) GB2081508B (enExample)
NL (1) NL8103031A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0147249B1 (en) * 1983-09-19 1989-01-18 Fairchild Semiconductor Corporation Method of manufacturing transistor structures having junctions bound by insulating layers, and resulting structures
JPH08213475A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置とその製造方法
EP0948046A1 (en) * 1998-03-26 1999-10-06 Texas Instruments Incorporated Merged bipolar and CMOS circuit and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4338622A (en) * 1979-06-29 1982-07-06 International Business Machines Corporation Self-aligned semiconductor circuits and process therefor
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact

Also Published As

Publication number Publication date
NL8103031A (nl) 1982-03-01
GB2081508A (en) 1982-02-17
DE3129487C2 (enExample) 1987-06-04
JPS5753973A (enExample) 1982-03-31
DE3129487A1 (de) 1982-06-24

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee