DE3068717D1 - Semiconductor memory device with redundancy - Google Patents
Semiconductor memory device with redundancyInfo
- Publication number
- DE3068717D1 DE3068717D1 DE8080303939T DE3068717T DE3068717D1 DE 3068717 D1 DE3068717 D1 DE 3068717D1 DE 8080303939 T DE8080303939 T DE 8080303939T DE 3068717 T DE3068717 T DE 3068717T DE 3068717 D1 DE3068717 D1 DE 3068717D1
- Authority
- DE
- Germany
- Prior art keywords
- redundancy
- memory cell
- memory device
- semiconductor memory
- decoders
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/806—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by reducing size of decoders
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979157393U JPS5928560Y2 (ja) | 1979-11-13 | 1979-11-13 | 冗長ビットを有する記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3068717D1 true DE3068717D1 (en) | 1984-08-30 |
Family
ID=15648645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8080303939T Expired DE3068717D1 (en) | 1979-11-13 | 1980-11-05 | Semiconductor memory device with redundancy |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4365319A (enExample) |
| EP (1) | EP0029322B1 (enExample) |
| JP (1) | JPS5928560Y2 (enExample) |
| DE (1) | DE3068717D1 (enExample) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS563499A (en) * | 1979-06-25 | 1981-01-14 | Fujitsu Ltd | Semiconductor memory device |
| US4489402A (en) * | 1981-04-25 | 1984-12-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
| US4462091A (en) * | 1982-02-26 | 1984-07-24 | International Business Machines Corporation | Word group redundancy scheme |
| JPS58164099A (ja) * | 1982-03-25 | 1983-09-28 | Toshiba Corp | 半導体メモリ− |
| JPS58199496A (ja) * | 1982-05-14 | 1983-11-19 | Hitachi Ltd | 欠陥救済回路を有する半導体メモリ |
| JPS5971199A (ja) * | 1982-10-14 | 1984-04-21 | Toshiba Corp | 半導体メモリ装置 |
| US4494220A (en) * | 1982-11-24 | 1985-01-15 | At&T Bell Laboratories | Folded bit line memory with one decoder per pair of spare rows |
| US4633429A (en) * | 1982-12-27 | 1986-12-30 | Motorola, Inc. | Partial memory selection using a programmable decoder |
| US4556975A (en) * | 1983-02-07 | 1985-12-03 | Westinghouse Electric Corp. | Programmable redundancy circuit |
| JPS59151398A (ja) * | 1983-02-17 | 1984-08-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US4577294A (en) * | 1983-04-18 | 1986-03-18 | Advanced Micro Devices, Inc. | Redundant memory circuit and method of programming and verifying the circuit |
| US4590388A (en) * | 1984-04-23 | 1986-05-20 | At&T Bell Laboratories | CMOS spare decoder circuit |
| JPS6143362A (ja) * | 1984-08-07 | 1986-03-01 | Nec Corp | 集積回路装置 |
| JPS6177946A (ja) * | 1984-09-26 | 1986-04-21 | Hitachi Ltd | 半導体記憶装置 |
| US4796233A (en) * | 1984-10-19 | 1989-01-03 | Fujitsu Limited | Bipolar-transistor type semiconductor memory device having redundancy configuration |
| US4744060A (en) * | 1984-10-19 | 1988-05-10 | Fujitsu Limited | Bipolar-transistor type random access memory having redundancy configuration |
| US4740925A (en) * | 1985-10-15 | 1988-04-26 | Texas Instruments Incorporated | Extra row for testing programmability and speed of ROMS |
| JPS62293598A (ja) * | 1986-06-12 | 1987-12-21 | Toshiba Corp | 半導体記憶装置 |
| JPS6337899A (ja) * | 1986-07-30 | 1988-02-18 | Mitsubishi Electric Corp | 半導体記憶装置 |
| EP0257120B1 (de) * | 1986-08-22 | 1992-06-10 | International Business Machines Corporation | Dekodierverfahren und -Schaltungsanordnung für einen redundanten CMOS-Halbleiterspeicher |
| FR2608826B1 (fr) * | 1986-12-19 | 1989-03-17 | Eurotechnique Sa | Circuit integre comportant des elements d'aiguillage vers des elements de redondance dans une memoire |
| US5191224A (en) * | 1987-04-22 | 1993-03-02 | Hitachi, Ltd. | Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein |
| FR2623653B1 (fr) * | 1987-11-24 | 1992-10-23 | Sgs Thomson Microelectronics | Procede de test de cellules de memoire electriquement programmable et circuit integre correspondant |
| US4885720A (en) * | 1988-04-01 | 1989-12-05 | International Business Machines Corporation | Memory device and method implementing wordline redundancy without an access time penalty |
| US5022006A (en) * | 1988-04-01 | 1991-06-04 | International Business Machines Corporation | Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells |
| US5289417A (en) * | 1989-05-09 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with redundancy circuit |
| JP2547633B2 (ja) * | 1989-05-09 | 1996-10-23 | 三菱電機株式会社 | 半導体記憶装置 |
| DE69129882T2 (de) * | 1990-06-19 | 1999-03-04 | Texas Instruments Inc., Dallas, Tex. | Assoziatives DRAM-Redundanzschema mit variabler Satzgrösse |
| JP2600018B2 (ja) * | 1990-09-29 | 1997-04-16 | 三菱電機株式会社 | 半導体記憶装置 |
| DE69117926D1 (de) * | 1991-03-29 | 1996-04-18 | Ibm | Speichersystem mit anpassbarer Redundanz |
| JP2738195B2 (ja) * | 1991-12-27 | 1998-04-08 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
| US5557618A (en) * | 1993-01-19 | 1996-09-17 | Tektronix, Inc. | Signal sampling circuit with redundancy |
| EP0657814B1 (en) * | 1993-12-07 | 1999-03-17 | STMicroelectronics S.r.l. | Redundancy circuitry for a semiconductor memory device |
| US5568433A (en) * | 1995-06-19 | 1996-10-22 | International Business Machines Corporation | Memory array having redundant word line |
| EP0798642B1 (en) * | 1996-03-29 | 2001-11-07 | STMicroelectronics S.r.l. | Redundancy management method and architecture, particularly for non-volatile memories |
| WO2004090910A1 (en) * | 2003-04-07 | 2004-10-21 | Koninklijke Philips Electronics N.V. | Semiconductor memory device having redundancy means |
| US10896127B2 (en) | 2013-01-23 | 2021-01-19 | Lucata Corporation | Highly configurable memory architecture for partitioned global address space memory systems |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3753244A (en) * | 1971-08-18 | 1973-08-14 | Ibm | Yield enhancement redundancy technique |
| BE789991A (fr) * | 1971-10-12 | 1973-04-12 | Siemens Ag | Dispositif logique, en particulier decodeur a elements redondants |
| US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
-
1979
- 1979-11-13 JP JP1979157393U patent/JPS5928560Y2/ja not_active Expired
-
1980
- 1980-11-05 EP EP80303939A patent/EP0029322B1/en not_active Expired
- 1980-11-05 DE DE8080303939T patent/DE3068717D1/de not_active Expired
- 1980-11-12 US US06/206,272 patent/US4365319A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4365319A (en) | 1982-12-21 |
| EP0029322B1 (en) | 1984-07-25 |
| JPS5677100U (enExample) | 1981-06-23 |
| JPS5928560Y2 (ja) | 1984-08-17 |
| EP0029322A1 (en) | 1981-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8331 | Complete revocation |