DE2944497C2 - - Google Patents

Info

Publication number
DE2944497C2
DE2944497C2 DE2944497A DE2944497A DE2944497C2 DE 2944497 C2 DE2944497 C2 DE 2944497C2 DE 2944497 A DE2944497 A DE 2944497A DE 2944497 A DE2944497 A DE 2944497A DE 2944497 C2 DE2944497 C2 DE 2944497C2
Authority
DE
Germany
Prior art keywords
signal
flip
flop
access
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2944497A
Other languages
German (de)
English (en)
Other versions
DE2944497A1 (de
Inventor
Vittorio Dipl.-Ing. Mailand/Milano It Zanchi
Tiziano Dipl.-Ing. Pregnana Milanese It Maccianti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of DE2944497A1 publication Critical patent/DE2944497A1/de
Application granted granted Critical
Publication of DE2944497C2 publication Critical patent/DE2944497C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
DE19792944497 1978-11-06 1979-11-03 Datenverarbeitungsanlage mit mehreren geraeteeinheiten Granted DE2944497A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT29453/78A IT1100916B (it) 1978-11-06 1978-11-06 Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati

Publications (2)

Publication Number Publication Date
DE2944497A1 DE2944497A1 (de) 1980-05-14
DE2944497C2 true DE2944497C2 (fr) 1989-03-23

Family

ID=11227017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792944497 Granted DE2944497A1 (de) 1978-11-06 1979-11-03 Datenverarbeitungsanlage mit mehreren geraeteeinheiten

Country Status (10)

Country Link
US (1) US4302808A (fr)
JP (1) JPS5585935A (fr)
AU (1) AU524538B2 (fr)
CA (1) CA1129109A (fr)
DE (1) DE2944497A1 (fr)
FR (1) FR2441215B1 (fr)
GB (1) GB2035636B (fr)
IL (1) IL58644A (fr)
IT (1) IT1100916B (fr)
YU (1) YU41492B (fr)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1149252B (it) * 1980-09-09 1986-12-03 Sits Soc It Telecom Siemens Modulo di ingresso-uscita per un elaboratore elettronico
US4556953A (en) * 1982-02-24 1985-12-03 Caprio A Ronald Interchangeable interface circuitry arrangements for use with a data processing system
IT1151683B (it) * 1982-07-06 1986-12-24 Honeywell Inf Systems Sistema multiprocessore a bus asincrono con caricamento di microistruzioni da memoria di lavoro
US4559595A (en) * 1982-12-27 1985-12-17 Honeywell Information Systems Inc. Distributed priority network logic for allowing a low priority unit to reside in a high priority position
AU562975B2 (en) * 1983-09-22 1987-06-25 Digital Equipment Corporation Message oriented interrupt mechanism for multiprocessor systems
US4769768A (en) * 1983-09-22 1988-09-06 Digital Equipment Corporation Method and apparatus for requesting service of interrupts by selected number of processors
US4787033A (en) * 1983-09-22 1988-11-22 Digital Equipment Corporation Arbitration mechanism for assigning control of a communications path in a digital computer system
SE445861B (sv) * 1984-12-12 1986-07-21 Ellemtel Utvecklings Ab Prioritetsfordelningsanordning for datorer
AU580359B2 (en) * 1984-12-12 1989-01-12 Telefonaktiebolaget Lm Ericsson (Publ) Arrangement for apportioning priority among co-operating computers
EP0199053B1 (fr) * 1985-03-20 1993-07-28 Hitachi, Ltd. Système de commande d'entrée/sortie
JPS61296458A (ja) * 1985-06-26 1986-12-27 Oki Electric Ind Co Ltd バス使用権決定方式
US4910655A (en) * 1985-08-14 1990-03-20 Apple Computer, Inc. Apparatus for transferring signals and data under the control of a host computer
US4875158A (en) * 1985-08-14 1989-10-17 Apple Computer, Inc. Method for requesting service by a device which generates a service request signal successively until it is serviced
US4918598A (en) * 1985-08-14 1990-04-17 Apple Computer, Inc. Method for selectively activating and deactivating devices having same first address and different extended addresses
US4912627A (en) * 1985-08-14 1990-03-27 Apple Computer, Inc. Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device
AU604063B2 (en) * 1987-10-13 1990-12-06 Honeywell Bull Inc. Circuit for preventing lock-out of high priority requests to a system controller
US4914580A (en) * 1987-10-26 1990-04-03 American Telephone And Telegraph Company Communication system having interrupts with dynamically adjusted priority levels
US5088053A (en) * 1987-11-16 1992-02-11 Intel Corporation Memory controller as for a video signal processor
US5003461A (en) * 1988-02-01 1991-03-26 Motorola, Inc. Cluster controller memory arbiter
JPH0268632A (ja) * 1988-09-05 1990-03-08 Toshiba Corp 割込み制御装置
US5276818A (en) * 1989-04-24 1994-01-04 Hitachi, Ltd. Bus system for information processing system and method of controlling the same
US5095460A (en) * 1989-04-25 1992-03-10 Digital Equipment Corporation Rotating priority encoder operating by selectively masking input signals to a fixed priority encoder
EP0464237A1 (fr) * 1990-07-03 1992-01-08 International Business Machines Corporation Schéma d'arbitrage de bus
US5265255A (en) * 1990-09-24 1993-11-23 International Business Machines Corp. Personal computer system with interrupt controller
US5251305A (en) * 1991-04-04 1993-10-05 Unisys Corporation Apparatus and method for preventing bus contention among a plurality of data sources
JP2625589B2 (ja) * 1991-04-22 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ・システム
US5805841A (en) * 1991-07-24 1998-09-08 Micron Electronics, Inc. Symmetric parallel multi-processing bus architeture
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
US5581770A (en) * 1992-06-04 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Floating interruption handling system and method
US5487170A (en) * 1993-12-16 1996-01-23 International Business Machines Corporation Data processing system having dynamic priority task scheduling capabilities
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
GB2341768A (en) * 1998-09-18 2000-03-22 Pixelfusion Ltd Bus arbitration
JP4887824B2 (ja) * 2006-02-16 2012-02-29 富士通セミコンダクター株式会社 メモリシステム
US9524312B2 (en) * 2009-04-29 2016-12-20 Ianywhere Solutions, Inc. Prioritized, incremental data retrieval from a database, with an event listener

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3471834A (en) * 1964-05-04 1969-10-07 Gen Electric Data processing unit for executing commands by external apparatus
US3445822A (en) * 1967-07-14 1969-05-20 Ibm Communication arrangement in data processing system
US3534339A (en) * 1967-08-24 1970-10-13 Burroughs Corp Service request priority resolver and encoder
US3611305A (en) * 1969-02-10 1971-10-05 Scanders Associates Inc Data processor interrupt system
US3611307A (en) * 1969-04-03 1971-10-05 Ibm Execution unit shared by plurality of arrays of virtual processors
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
GB1356269A (en) * 1971-09-25 1974-06-12 Ibm Digital data handling system
US3832692A (en) * 1972-06-27 1974-08-27 Honeywell Inf Systems Priority network for devices coupled by a multi-line bus
US3800287A (en) * 1972-06-27 1974-03-26 Honeywell Inf Systems Data processing system having automatic interrupt identification technique
IT971304B (it) * 1972-11-29 1974-04-30 Honeywell Inf Systems Sistema di accesso a priorita variabile dinamicamente
US3866181A (en) * 1972-12-26 1975-02-11 Honeywell Inf Systems Interrupt sequencing control apparatus
IT1002275B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di elaborazione dati a piu canali di ingresso uscita a risorse orientate per livelli di servizio distinti e interrompi bili
US3967246A (en) * 1974-06-05 1976-06-29 Bell Telephone Laboratories, Incorporated Digital computer arrangement for communicating data via data buses
JPS5126426A (fr) * 1974-08-30 1976-03-04 Hitachi Ltd
US3983540A (en) * 1975-09-08 1976-09-28 Honeywell Inc. Rapid bus priority resolution
JPS5837585B2 (ja) * 1975-09-30 1983-08-17 株式会社東芝 ケイサンキソウチ
JPS5259534A (en) * 1975-11-11 1977-05-17 Panafacom Ltd Data transfer system
US4038644A (en) * 1975-11-19 1977-07-26 Ncr Corporation Destination selection apparatus for a bus oriented computer system
JPS52132748A (en) * 1976-04-30 1977-11-07 Hitachi Ltd Information i/o control system
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4096569A (en) * 1976-12-27 1978-06-20 Honeywell Information Systems Inc. Data processing system having distributed priority network with logic for deactivating information transfer requests
US4148011A (en) * 1977-06-06 1979-04-03 General Automation, Inc. Asynchronous priority circuit for controlling access to a bus
IT1093493B (it) * 1978-03-23 1985-07-19 Honeywell Inf Systems Circuito di trasmissione bidirezionale di segnali interbloccati

Also Published As

Publication number Publication date
GB2035636A (en) 1980-06-18
IT7829453A0 (it) 1978-11-06
AU5243079A (en) 1980-05-15
DE2944497A1 (de) 1980-05-14
JPS5585935A (en) 1980-06-28
FR2441215B1 (fr) 1985-12-27
IT1100916B (it) 1985-09-28
YU270079A (en) 1983-04-30
YU41492B (en) 1987-08-31
IL58644A (en) 1982-08-31
GB2035636B (en) 1983-01-06
AU524538B2 (en) 1982-09-23
FR2441215A1 (fr) 1980-06-06
US4302808A (en) 1981-11-24
CA1129109A (fr) 1982-08-03

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee