GB1356269A - Digital data handling system - Google Patents

Abstract

1356269 Interrupt handling INTERNATIONAL BUSINESS MACHINES CORP 25 Sept 1971 44775/71 Heading G4A A data handling system comprises a controller 1 and a plurality of input/output modules connected in a loop between a first interrupt condition terminal 4A and a second interrupt condition terminal 4B on the controller by means of a sequence line 2 which enters each module by a first terminal and leaves it by a second terminal, each module being adapted to energize one and both terminals in response to first and second interrupt conditions respectively, to transmit from each terminal signals received at the other, and to respond to the signals applied to the sequence line by the other modules to develop a signal indicative of the priority of an interrupt condition requiring energization of one or both of its terminals relative to the priority of similar conditions occurring within other modules. Two categories of interrupt, high and low, may be serviced by the system with the modules arranged in descending order of priority within the high category M 1 , M 2 ..., M n and in descending order Mn, M n-1 , ..., M 1 , in the low category. Each module contains two bi-stables with outputs H and L, H being set to 1 for a high level interrupt and L for a low level interrupt in the corresponding module. A further bi-stable generates a signal Z indicating that the module is generating the highest level priority interrupt within the system and must therefore transfer its identity, over line 2, to the controller. When a module generates a high level interrupt it transmits a signal in both directions and when it generates a low level interrupt it transmits it only towards terminal 4A. The value Z within a module must be 1 when that module generates a high level interrupt if no high level interrupt exists on its left and when it generates a low level interrupt if no interrupts of either category exist to its right and no high level interrupt exists to its left i.e.: Each module transmits from each of its terminals signals received from other modules at the other terminal so that: Pi = 1 when Pi + 1 = 1 and Qi= 1 when Qi - 1 = 1. To implement these equations a module must detect the value of Q to its left and of P to its right and a transistor circuit is described to accomplish this by detecting the potential and direction of current flow in the two segments of sequence line to which the module is connected. A circuit is also described for use in the controller for detecting when P 1 = Q n = 1, i.e. a high level interrupt is present, and P 1 = 1 and Qn = 0, i.e. a low level interrupt is present.