GB1356269A - Digital data handling system - Google Patents
Digital data handling systemInfo
- Publication number
- GB1356269A GB1356269A GB4477571A GB4477571A GB1356269A GB 1356269 A GB1356269 A GB 1356269A GB 4477571 A GB4477571 A GB 4477571A GB 4477571 A GB4477571 A GB 4477571A GB 1356269 A GB1356269 A GB 1356269A
- Authority
- GB
- United Kingdom
- Prior art keywords
- interrupt
- module
- terminal
- level interrupt
- high level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/423—Loop networks with centralised control, e.g. polling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Bus Control (AREA)
Abstract
1356269 Interrupt handling INTERNATIONAL BUSINESS MACHINES CORP 25 Sept 1971 44775/71 Heading G4A A data handling system comprises a controller 1 and a plurality of input/output modules connected in a loop between a first interrupt condition terminal 4A and a second interrupt condition terminal 4B on the controller by means of a sequence line 2 which enters each module by a first terminal and leaves it by a second terminal, each module being adapted to energize one and both terminals in response to first and second interrupt conditions respectively, to transmit from each terminal signals received at the other, and to respond to the signals applied to the sequence line by the other modules to develop a signal indicative of the priority of an interrupt condition requiring energization of one or both of its terminals relative to the priority of similar conditions occurring within other modules. Two categories of interrupt, high and low, may be serviced by the system with the modules arranged in descending order of priority within the high category M 1 , M 2 ..., M n and in descending order Mn, M n-1 , ..., M 1 , in the low category. Each module contains two bi-stables with outputs H and L, H being set to 1 for a high level interrupt and L for a low level interrupt in the corresponding module. A further bi-stable generates a signal Z indicating that the module is generating the highest level priority interrupt within the system and must therefore transfer its identity, over line 2, to the controller. When a module generates a high level interrupt it transmits a signal in both directions and when it generates a low level interrupt it transmits it only towards terminal 4A. The value Z within a module must be 1 when that module generates a high level interrupt if no high level interrupt exists on its left and when it generates a low level interrupt if no interrupts of either category exist to its right and no high level interrupt exists to its left i.e.: Each module transmits from each of its terminals signals received from other modules at the other terminal so that: Pi = 1 when Pi + 1 = 1 and Qi= 1 when Qi - 1 = 1. To implement these equations a module must detect the value of Q to its left and of P to its right and a transistor circuit is described to accomplish this by detecting the potential and direction of current flow in the two segments of sequence line to which the module is connected. A circuit is also described for use in the controller for detecting when P 1 = Q n = 1, i.e. a high level interrupt is present, and P 1 = 1 and Qn = 0, i.e. a low level interrupt is present.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4477571A GB1356269A (en) | 1971-09-25 | 1971-09-25 | Digital data handling system |
DE19722234407 DE2234407C2 (en) | 1971-09-25 | 1972-07-13 | Data processing system |
IT2748972A IT963422B (en) | 1971-09-25 | 1972-07-27 | NUMERICAL SYSTEM FOR DATA PROCESSING |
JP47083824A JPS5118772B2 (en) | 1971-09-25 | 1972-08-23 | |
FR7233191A FR2154128A5 (en) | 1971-09-25 | 1972-09-12 | |
CA152,309A CA955689A (en) | 1971-09-25 | 1972-09-22 | Digital data handling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4477571A GB1356269A (en) | 1971-09-25 | 1971-09-25 | Digital data handling system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1356269A true GB1356269A (en) | 1974-06-12 |
Family
ID=10434687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4477571A Expired GB1356269A (en) | 1971-09-25 | 1971-09-25 | Digital data handling system |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5118772B2 (en) |
CA (1) | CA955689A (en) |
DE (1) | DE2234407C2 (en) |
FR (1) | FR2154128A5 (en) |
GB (1) | GB1356269A (en) |
IT (1) | IT963422B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51104002U (en) * | 1975-02-17 | 1976-08-20 | ||
GB1508854A (en) * | 1975-07-04 | 1978-04-26 | Ibm | Data handling system |
DE2744111A1 (en) * | 1977-09-30 | 1979-04-05 | Siemens Ag | CIRCUIT ARRANGEMENT FOR THE INPUT OF INTERRUPTION COMMANDS AND OUTPUT OF INTERRUPTION CONFIRMATIONS FOR COMPUTER SYSTEMS |
JPS5846098B2 (en) * | 1978-10-30 | 1983-10-14 | 株式会社日立製作所 | Bus priority control method in loop bus network system |
IT1100916B (en) * | 1978-11-06 | 1985-09-28 | Honeywell Inf Systems | APPARATUS FOR MANAGEMENT OF DATA TRANSFER REQUESTS IN DATA PROCESSING SYSTEMS |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1228550A (en) * | 1969-04-30 | 1971-04-15 |
-
1971
- 1971-09-25 GB GB4477571A patent/GB1356269A/en not_active Expired
-
1972
- 1972-07-13 DE DE19722234407 patent/DE2234407C2/en not_active Expired
- 1972-07-27 IT IT2748972A patent/IT963422B/en active
- 1972-08-23 JP JP47083824A patent/JPS5118772B2/ja not_active Expired
- 1972-09-12 FR FR7233191A patent/FR2154128A5/fr not_active Expired
- 1972-09-22 CA CA152,309A patent/CA955689A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5118772B2 (en) | 1976-06-12 |
DE2234407C2 (en) | 1982-04-01 |
DE2234407A1 (en) | 1973-03-29 |
CA955689A (en) | 1974-10-01 |
FR2154128A5 (en) | 1973-05-04 |
IT963422B (en) | 1974-01-10 |
JPS4841644A (en) | 1973-06-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |