DE2822011B2 - Halbleiteranordnung und Verfahren zu deren Herstellung - Google Patents
Halbleiteranordnung und Verfahren zu deren HerstellungInfo
- Publication number
- DE2822011B2 DE2822011B2 DE19782822011 DE2822011A DE2822011B2 DE 2822011 B2 DE2822011 B2 DE 2822011B2 DE 19782822011 DE19782822011 DE 19782822011 DE 2822011 A DE2822011 A DE 2822011A DE 2822011 B2 DE2822011 B2 DE 2822011B2
- Authority
- DE
- Germany
- Prior art keywords
- power supply
- supply bus
- wiring
- bus line
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19782822011 DE2822011B2 (de) | 1978-05-19 | 1978-05-19 | Halbleiteranordnung und Verfahren zu deren Herstellung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19782822011 DE2822011B2 (de) | 1978-05-19 | 1978-05-19 | Halbleiteranordnung und Verfahren zu deren Herstellung |
Publications (3)
Publication Number | Publication Date |
---|---|
DE2822011A1 DE2822011A1 (de) | 1979-11-22 |
DE2822011B2 true DE2822011B2 (de) | 1980-06-04 |
DE2822011C3 DE2822011C3 (US06653308-20031125-C00197.png) | 1987-09-10 |
Family
ID=6039783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19782822011 Granted DE2822011B2 (de) | 1978-05-19 | 1978-05-19 | Halbleiteranordnung und Verfahren zu deren Herstellung |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE2822011B2 (US06653308-20031125-C00197.png) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2495835A1 (fr) * | 1980-12-05 | 1982-06-11 | Cii Honeywell Bull | Dispositif a circuits integres a reseau metallique d'interconnexion, et procede de fabrication de ce dispositif |
DE3315615A1 (de) * | 1983-04-29 | 1984-10-31 | Brown, Boveri & Cie Ag, 6800 Mannheim | Verfahren zur herstellung einer multilayer-schaltung |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3053926A (en) * | 1959-12-14 | 1962-09-11 | Int Rectifier Corp | Silicon photoelectric cell |
USB392136I5 (US06653308-20031125-C00197.png) * | 1964-08-26 | |||
DE1764269A1 (de) * | 1968-05-07 | 1971-06-16 | Siemens Ag | Verfahren zum Herstellen von Planarbauelementen,insbesondere von fuer hohe Frequenzen zu verwendende Germanium-Planartransistoren |
DE1790025B1 (de) * | 1968-08-29 | 1972-05-04 | Siemens Ag | Verfahren zur herstellung galvanisch verstaerkter m etallischer mikrostrukturen |
CA1024661A (en) * | 1974-06-26 | 1978-01-17 | International Business Machines Corporation | Wireable planar integrated circuit chip structure |
-
1978
- 1978-05-19 DE DE19782822011 patent/DE2822011B2/de active Granted
Also Published As
Publication number | Publication date |
---|---|
DE2822011C3 (US06653308-20031125-C00197.png) | 1987-09-10 |
DE2822011A1 (de) | 1979-11-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OAP | Request for examination filed | ||
OD | Request for examination | ||
8281 | Inventor (new situation) |
Free format text: MOGI, JUN-ICHI, KAWASAKI, KANAGAWA, JP MIYASAKA, KIYOSHI ABIRU, AKIRA, YOKOHAMA, KANAGAWA, JP ITO, KATSUFUMI, TOKIO/TOKYO, JP |
|
C3 | Grant after two publication steps (3rd publication) | ||
8339 | Ceased/non-payment of the annual fee |