DE2728167A1 - Verfahren zur vorbereitung eines siliziumsubstrats fuer die herstellung von mos-bauelementen - Google Patents

Verfahren zur vorbereitung eines siliziumsubstrats fuer die herstellung von mos-bauelementen

Info

Publication number
DE2728167A1
DE2728167A1 DE19772728167 DE2728167A DE2728167A1 DE 2728167 A1 DE2728167 A1 DE 2728167A1 DE 19772728167 DE19772728167 DE 19772728167 DE 2728167 A DE2728167 A DE 2728167A DE 2728167 A1 DE2728167 A1 DE 2728167A1
Authority
DE
Germany
Prior art keywords
substrate
dopant
zones
zone
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19772728167
Other languages
German (de)
English (en)
Inventor
Richard D Pashley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE2728167A1 publication Critical patent/DE2728167A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE19772728167 1976-06-25 1977-06-23 Verfahren zur vorbereitung eines siliziumsubstrats fuer die herstellung von mos-bauelementen Ceased DE2728167A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/700,043 US4052229A (en) 1976-06-25 1976-06-25 Process for preparing a substrate for mos devices of different thresholds

Publications (1)

Publication Number Publication Date
DE2728167A1 true DE2728167A1 (de) 1978-01-05

Family

ID=24811961

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772728167 Ceased DE2728167A1 (de) 1976-06-25 1977-06-23 Verfahren zur vorbereitung eines siliziumsubstrats fuer die herstellung von mos-bauelementen

Country Status (2)

Country Link
US (1) US4052229A (enExample)
DE (1) DE2728167A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019886A1 (de) * 1979-05-30 1980-12-10 Siemens Aktiengesellschaft Halbleiterspeicher

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US4205330A (en) * 1977-04-01 1980-05-27 National Semiconductor Corporation Method of manufacturing a low voltage n-channel MOSFET device
US4131497A (en) * 1977-07-12 1978-12-26 International Business Machines Corporation Method of manufacturing self-aligned semiconductor devices
JPS605108B2 (ja) * 1977-08-01 1985-02-08 株式会社日立製作所 固体擦像装置
US4178605A (en) * 1978-01-30 1979-12-11 Rca Corp. Complementary MOS inverter structure
US4178674A (en) * 1978-03-27 1979-12-18 Intel Corporation Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor
US4212683A (en) * 1978-03-27 1980-07-15 Ncr Corporation Method for making narrow channel FET
US4485390A (en) * 1978-03-27 1984-11-27 Ncr Corporation Narrow channel FET
US4481704A (en) * 1978-04-21 1984-11-13 Texas Instruments Incorporated Method of making an improved MESFET semiconductor device
US4223334A (en) * 1978-08-29 1980-09-16 Harris Corporation High voltage CMOS with local oxidation for self-aligned guard rings and process of fabrication
US4472871A (en) * 1978-09-21 1984-09-25 Mostek Corporation Method of making a plurality of MOSFETs having different threshold voltages
JPS5548894A (en) * 1978-09-29 1980-04-08 Nec Corp Memory circuit
CA1131367A (en) * 1978-11-13 1982-09-07 Keming W. Yeh Self-aligned mesfet having reduced series resistance
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4244752A (en) * 1979-03-06 1981-01-13 Burroughs Corporation Single mask method of fabricating complementary integrated circuits
US4218267A (en) * 1979-04-23 1980-08-19 Rockwell International Corporation Microelectronic fabrication method minimizing threshold voltage variation
CA1151295A (en) * 1979-07-31 1983-08-02 Alan Aitken Dual resistivity mos devices and method of fabrication
US4261761A (en) * 1979-09-04 1981-04-14 Tektronix, Inc. Method of manufacturing sub-micron channel width MOS transistor
US4257826A (en) * 1979-10-11 1981-03-24 Texas Instruments Incorporated Photoresist masking in manufacture of semiconductor device
US4322823A (en) * 1980-03-03 1982-03-30 International Business Machines Corp. Storage system having bilateral field effect transistor personalization
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
US4315781A (en) * 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
JPS5771581A (en) * 1980-10-22 1982-05-04 Toshiba Corp Active boosting circuit
US4521796A (en) * 1980-12-11 1985-06-04 General Instrument Corporation Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device
DE3108726A1 (de) * 1981-03-07 1982-09-16 Deutsche Itt Industries Gmbh, 7800 Freiburg Monolithisch integrierte referenzspannungsquelle
US4397076A (en) * 1981-09-14 1983-08-09 Ncr Corporation Method for making low leakage polycrystalline silicon-to-substrate contacts
US4609833A (en) * 1983-08-12 1986-09-02 Thomson Components-Mostek Corporation Simple NMOS voltage reference circuit
US4618815A (en) * 1985-02-11 1986-10-21 At&T Bell Laboratories Mixed threshold current mirror
US4992838A (en) * 1988-02-29 1991-02-12 Texas Instruments Incorporated Vertical MOS transistor with threshold voltage adjustment
JP2509707B2 (ja) * 1989-09-04 1996-06-26 株式会社東芝 半導体装置の製造方法
US5095348A (en) * 1989-10-02 1992-03-10 Texas Instruments Incorporated Semiconductor on insulator transistor
US5109187A (en) * 1990-09-28 1992-04-28 Intel Corporation CMOS voltage reference
US5244823A (en) * 1991-05-21 1993-09-14 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device
US5221635A (en) * 1991-12-17 1993-06-22 Texas Instruments Incorporated Method of making a field-effect transistor
US5369041A (en) * 1993-07-14 1994-11-29 Texas Instruments Incorporated Method for forming a silicon controlled rectifier
JP3584338B2 (ja) * 1994-03-03 2004-11-04 ローム・ユーエスエー・インク 電気的に消去及びプログラム可能なデバイスの消去方法
US5962898A (en) * 1994-04-11 1999-10-05 Texas Instruments Incorporated Field-effect transistor
US5675165A (en) * 1994-08-02 1997-10-07 Lien; Chuen-Der Stable SRAM cell using low backgate biased threshold voltage select transistors
US5671179A (en) * 1994-10-19 1997-09-23 Intel Corporation Low power pulse generator for smart voltage flash eeprom
US5585297A (en) * 1995-05-25 1996-12-17 United Microelectronics Corporation Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby
JP4207307B2 (ja) * 1999-04-26 2009-01-14 日新イオン機器株式会社 チャージアップ測定装置
US20080099852A1 (en) * 2006-10-31 2008-05-01 Juergen Faul Integrated semiconductor device and method of manufacturing an integrated semiconductor device

Citations (1)

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US3868274A (en) * 1974-01-02 1975-02-25 Gen Instrument Corp Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate

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GB1261723A (en) * 1968-03-11 1972-01-26 Associated Semiconductor Mft Improvements in and relating to semiconductor devices
US3731372A (en) * 1970-04-10 1973-05-08 Itt Method of forming a low-ohmic contact to a semiconductor device
US3775191A (en) * 1971-06-28 1973-11-27 Bell Canada Northern Electric Modification of channel regions in insulated gate field effect transistors
US3959040A (en) * 1971-09-01 1976-05-25 Motorola, Inc. Compound diffused regions for emitter-coupled logic circuits
US3756861A (en) * 1972-03-13 1973-09-04 Bell Telephone Labor Inc Bipolar transistors and method of manufacture
US3916430A (en) * 1973-03-14 1975-10-28 Rca Corp System for eliminating substrate bias effect in field effect transistor circuits
US3898105A (en) * 1973-10-25 1975-08-05 Mostek Corp Method for making FET circuits
US3928082A (en) * 1973-12-28 1975-12-23 Texas Instruments Inc Self-aligned transistor process

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US3868274A (en) * 1974-01-02 1975-02-25 Gen Instrument Corp Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate
US3868274B1 (enExample) * 1974-01-02 1988-07-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019886A1 (de) * 1979-05-30 1980-12-10 Siemens Aktiengesellschaft Halbleiterspeicher

Also Published As

Publication number Publication date
US4052229A (en) 1977-10-04
US4052229B1 (enExample) 1985-01-15

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Legal Events

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8110 Request for examination paragraph 44
8131 Rejection