DE2641024A1 - Verfahren zur herabsetzung der fehlstellendichte einer integrierten schaltung - Google Patents

Verfahren zur herabsetzung der fehlstellendichte einer integrierten schaltung

Info

Publication number
DE2641024A1
DE2641024A1 DE19762641024 DE2641024A DE2641024A1 DE 2641024 A1 DE2641024 A1 DE 2641024A1 DE 19762641024 DE19762641024 DE 19762641024 DE 2641024 A DE2641024 A DE 2641024A DE 2641024 A1 DE2641024 A1 DE 2641024A1
Authority
DE
Germany
Prior art keywords
layer
buried
formation
areas
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762641024
Other languages
German (de)
English (en)
Inventor
Bohumil Polata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of DE2641024A1 publication Critical patent/DE2641024A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H10P30/204—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H10P30/212—
    • H10W15/00—
    • H10W15/01—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/039—Displace P-N junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE19762641024 1975-09-22 1976-09-11 Verfahren zur herabsetzung der fehlstellendichte einer integrierten schaltung Withdrawn DE2641024A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/615,481 US3976512A (en) 1975-09-22 1975-09-22 Method for reducing the defect density of an integrated circuit utilizing ion implantation

Publications (1)

Publication Number Publication Date
DE2641024A1 true DE2641024A1 (de) 1977-03-31

Family

ID=24465561

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762641024 Withdrawn DE2641024A1 (de) 1975-09-22 1976-09-11 Verfahren zur herabsetzung der fehlstellendichte einer integrierten schaltung

Country Status (6)

Country Link
US (1) US3976512A (show.php)
JP (1) JPS5239386A (show.php)
CA (1) CA1046168A (show.php)
DE (1) DE2641024A1 (show.php)
FR (1) FR2325190A1 (show.php)
GB (1) GB1551129A (show.php)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4262056A (en) * 1978-09-15 1981-04-14 The United States Of America As Represented By The Secretary Of The Navy Ion-implanted multilayer optical interference filter
JPS5617011A (en) * 1979-07-23 1981-02-18 Toshiba Corp Semiconductor device and manufacture thereof
NL188432C (nl) * 1980-12-26 1992-06-16 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een mosfet.
US4416708A (en) * 1982-01-15 1983-11-22 International Rectifier Corporation Method of manufacture of high speed, high power bipolar transistor
US4571275A (en) * 1983-12-19 1986-02-18 International Business Machines Corporation Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector
JPS60130844A (ja) * 1983-12-20 1985-07-12 Toshiba Corp 半導体装置の製造方法
US4548658A (en) * 1985-01-30 1985-10-22 Cook Melvin S Growth of lattice-graded epilayers
US4644383A (en) * 1985-04-08 1987-02-17 Harris Corporation Subcollector for oxide and junction isolated IC's
US4695868A (en) * 1985-12-13 1987-09-22 Rca Corporation Patterned metallization for integrated circuits
US5156995A (en) * 1988-04-01 1992-10-20 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers
US5250445A (en) * 1988-12-20 1993-10-05 Texas Instruments Incorporated Discretionary gettering of semiconductor circuits
US5207863A (en) * 1990-04-06 1993-05-04 Canon Kabushiki Kaisha Crystal growth method and crystalline article obtained by said method
EP0584436A1 (en) * 1992-08-26 1994-03-02 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for forming buried regions, having different doping concentration, in monolitic semiconductor devices
US6316336B1 (en) * 1999-03-01 2001-11-13 Richard A. Blanchard Method for forming buried layers with top-side contacts and the resulting structure
DE102004051081A1 (de) * 2004-10-19 2006-04-27 Austriamicrosystems Ag JFET und Herstellungsverfahren
TW201029073A (en) * 2009-01-21 2010-08-01 Univ Nat Chunghsing Epitaxial wafer with low surface defect density
JP2019062139A (ja) * 2017-09-28 2019-04-18 豊田合成株式会社 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL297820A (show.php) * 1962-10-05
US3283223A (en) * 1963-12-27 1966-11-01 Ibm Transistor and method of fabrication to minimize surface recombination effects
FR1495766A (show.php) * 1965-12-10 1967-12-20
US3510736A (en) * 1967-11-17 1970-05-05 Rca Corp Integrated circuit planar transistor
NL6911771A (show.php) * 1968-08-14 1970-02-17
US3600241A (en) * 1968-09-09 1971-08-17 Ibm Method of fabricating semiconductor devices by diffusion
US3717790A (en) * 1971-06-24 1973-02-20 Bell Telephone Labor Inc Ion implanted silicon diode array targets for electron beam camera tubes
US3902926A (en) * 1974-02-21 1975-09-02 Signetics Corp Method of making an ion implanted resistor
NL163898C (nl) * 1974-03-16 1980-10-15 Nippon Musical Instruments Mfg Werkwijze voor het vervaardigen van een veldeffect- transistor met onverzadigde stroom-spanningskarakteri- stieken.
US3916431A (en) * 1974-06-21 1975-10-28 Rca Corp Bipolar integrated circuit transistor with lightly doped subcollector core

Also Published As

Publication number Publication date
FR2325190A1 (fr) 1977-04-15
GB1551129A (en) 1979-08-22
US3976512A (en) 1976-08-24
JPS5239386A (en) 1977-03-26
JPS5415754B2 (show.php) 1979-06-16
CA1046168A (en) 1979-01-09

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: MEIER, F., DIPL.-ING., PAT.-ANW., 2000 HAMBURG

8139 Disposal/non-payment of the annual fee