DE2628407C2 - Verfahren zum Herstellen von dielektrischen Isolationszonen - Google Patents

Verfahren zum Herstellen von dielektrischen Isolationszonen

Info

Publication number
DE2628407C2
DE2628407C2 DE2628407A DE2628407A DE2628407C2 DE 2628407 C2 DE2628407 C2 DE 2628407C2 DE 2628407 A DE2628407 A DE 2628407A DE 2628407 A DE2628407 A DE 2628407A DE 2628407 C2 DE2628407 C2 DE 2628407C2
Authority
DE
Germany
Prior art keywords
silicon
layer
openings
silicon dioxide
depressions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2628407A
Other languages
German (de)
English (en)
Other versions
DE2628407A1 (de
Inventor
Igor Pleasant Valley N.Y. Antipov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2628407A1 publication Critical patent/DE2628407A1/de
Application granted granted Critical
Publication of DE2628407C2 publication Critical patent/DE2628407C2/de
Expired legal-status Critical Current

Links

Classifications

    • H10W10/0142—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H10P95/00—
    • H10W10/17—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE2628407A 1975-06-30 1976-06-24 Verfahren zum Herstellen von dielektrischen Isolationszonen Expired DE2628407C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/592,015 US3961999A (en) 1975-06-30 1975-06-30 Method for forming recessed dielectric isolation with a minimized "bird's beak" problem

Publications (2)

Publication Number Publication Date
DE2628407A1 DE2628407A1 (de) 1977-01-20
DE2628407C2 true DE2628407C2 (de) 1982-10-21

Family

ID=24368923

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2628407A Expired DE2628407C2 (de) 1975-06-30 1976-06-24 Verfahren zum Herstellen von dielektrischen Isolationszonen

Country Status (7)

Country Link
US (1) US3961999A (OSRAM)
JP (1) JPS525288A (OSRAM)
CA (1) CA1043473A (OSRAM)
DE (1) DE2628407C2 (OSRAM)
FR (1) FR2316735A1 (OSRAM)
GB (1) GB1493212A (OSRAM)
IT (1) IT1063394B (OSRAM)

Families Citing this family (46)

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US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
JPS5253679A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Productin of semiconductor device
US4187125A (en) * 1976-12-27 1980-02-05 Raytheon Company Method for manufacturing semiconductor structures by anisotropic and isotropic etching
CA1090006A (en) * 1976-12-27 1980-11-18 Wolfgang M. Feist Semiconductor structures and methods for manufacturing such structures
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
US4131497A (en) * 1977-07-12 1978-12-26 International Business Machines Corporation Method of manufacturing self-aligned semiconductor devices
JPS54115085A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS55156366A (en) * 1979-05-24 1980-12-05 Toshiba Corp Semiconductor device
US4261761A (en) * 1979-09-04 1981-04-14 Tektronix, Inc. Method of manufacturing sub-micron channel width MOS transistor
NL7907434A (nl) * 1979-10-08 1981-04-10 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting.
US4303933A (en) * 1979-11-29 1981-12-01 International Business Machines Corporation Self-aligned micrometer bipolar transistor device and process
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US4465705A (en) * 1980-05-19 1984-08-14 Matsushita Electric Industrial Co., Ltd. Method of making semiconductor devices
JPS5735341A (en) * 1980-08-12 1982-02-25 Toshiba Corp Method of seperating elements of semiconductor device
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4658497A (en) * 1983-01-03 1987-04-21 Rca Corporation Method of making an imaging array having a higher sensitivity
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4505026A (en) * 1983-07-14 1985-03-19 Intel Corporation CMOS Process for fabricating integrated circuits, particularly dynamic memory cells
JPS6054453A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
US4691222A (en) * 1984-03-12 1987-09-01 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
US4612701A (en) * 1984-03-12 1986-09-23 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
US4749662A (en) * 1984-12-14 1988-06-07 Rockwell International Corporation Diffused field CMOS-bulk process
JPS6281727A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd 埋込型素子分離溝の形成方法
US4685194A (en) * 1985-10-21 1987-08-11 The United States Of America As Represented By The Secretary Of The Air Force Direct moat self-aligned field oxide technique
US4775644A (en) * 1987-06-03 1988-10-04 Lsi Logic Corporation Zero bird-beak oxide isolation scheme for integrated circuits
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JP2886183B2 (ja) * 1988-06-28 1999-04-26 三菱電機株式会社 フィールド分離絶縁膜の製造方法
NL8801772A (nl) * 1988-07-13 1990-02-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op een oppervlak van een halfgeleiderlichaam geisoleerde geleidersporen worden aangebracht.
US4948456A (en) * 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
US5045151A (en) * 1989-10-17 1991-09-03 Massachusetts Institute Of Technology Micromachined bonding surfaces and method of forming the same
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
US5175123A (en) * 1990-11-13 1992-12-29 Motorola, Inc. High-pressure polysilicon encapsulated localized oxidation of silicon
US5246537A (en) * 1992-04-30 1993-09-21 Motorola, Inc. Method of forming recessed oxide isolation
US5455194A (en) * 1995-03-06 1995-10-03 Motorola Inc. Encapsulation method for localized oxidation of silicon with trench isolation
KR100215843B1 (ko) * 1996-10-24 1999-08-16 구본준 반도체 소자의 격리층 형성 방법
KR100216266B1 (ko) * 1996-12-26 1999-08-16 구본준 반도체 장치의 제조방법
TW358236B (en) * 1997-12-19 1999-05-11 Nanya Technology Corp Improved local silicon oxidization method in the manufacture of semiconductor isolation
DE102007046557A1 (de) * 2007-09-28 2009-04-02 Infineon Technologies Austria Ag Halbleiterstruktur mit verfüllter Ausnehmung
US8772902B2 (en) 2012-04-19 2014-07-08 International Business Machines Corporation Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3424629A (en) * 1965-12-13 1969-01-28 Ibm High capacity epitaxial apparatus and method
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
NL166156C (nl) * 1971-05-22 1981-06-15 Philips Nv Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan.
NL7204741A (OSRAM) * 1972-04-08 1973-10-10
US3858231A (en) * 1973-04-16 1974-12-31 Ibm Dielectrically isolated schottky barrier structure and method of forming the same
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US3886000A (en) * 1973-11-05 1975-05-27 Ibm Method for controlling dielectric isolation of a semiconductor device

Also Published As

Publication number Publication date
FR2316735A1 (fr) 1977-01-28
CA1043473A (en) 1978-11-28
JPS5346703B2 (OSRAM) 1978-12-15
FR2316735B1 (OSRAM) 1978-11-17
GB1493212A (en) 1977-11-30
JPS525288A (en) 1977-01-14
US3961999A (en) 1976-06-08
IT1063394B (it) 1985-02-11
DE2628407A1 (de) 1977-01-20

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Legal Events

Date Code Title Description
OD Request for examination
D2 Grant after examination
8339 Ceased/non-payment of the annual fee