DE2456742A1 - Verfahren zur erzeugung des n-fachen einer normalfrequenz - Google Patents
Verfahren zur erzeugung des n-fachen einer normalfrequenzInfo
- Publication number
- DE2456742A1 DE2456742A1 DE19742456742 DE2456742A DE2456742A1 DE 2456742 A1 DE2456742 A1 DE 2456742A1 DE 19742456742 DE19742456742 DE 19742456742 DE 2456742 A DE2456742 A DE 2456742A DE 2456742 A1 DE2456742 A1 DE 2456742A1
- Authority
- DE
- Germany
- Prior art keywords
- frequency
- pulse
- counter
- phase
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 238000012544 monitoring process Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000001960 triggered effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH1788973A CH566089A5 (US06330241-20011211-M00004.png) | 1973-12-20 | 1973-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2456742A1 true DE2456742A1 (de) | 1975-06-26 |
Family
ID=4428858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19742456742 Pending DE2456742A1 (de) | 1973-12-20 | 1974-11-30 | Verfahren zur erzeugung des n-fachen einer normalfrequenz |
Country Status (7)
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2502435A1 (fr) * | 1981-03-20 | 1982-09-24 | Victor Company Of Japan | Dispositif multiplicateur de la frequence de balayage horizontal |
| EP0089372A1 (en) * | 1981-09-28 | 1983-09-28 | Honeywell Inc. | System for preventing transient induced errors in phase locked loop |
| FR2526619A1 (fr) * | 1982-05-06 | 1983-11-10 | Victor Company Of Japan | Circuit de multiplication de la frequence de balayage |
| EP0645892A1 (fr) * | 1993-09-28 | 1995-03-29 | France Telecom | Dispositif d'asservissement de fréquence |
| WO1995018508A1 (en) * | 1993-12-29 | 1995-07-06 | Zenith Electronics Corporation | Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator |
| WO1997023049A1 (en) * | 1995-12-20 | 1997-06-26 | Italtel S.P.A. | Procedure and circuit for holding lock state in a digital pll |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE7411960L (sv) * | 1974-09-24 | 1976-03-25 | Fabriker As Haustrups | Sett att framstella behallare sasom flaskor eller burkar av polyester |
| US4290028A (en) * | 1979-07-30 | 1981-09-15 | International Telephone And Telegraph Corporation | High speed phase locked loop frequency synthesizer |
| JPS5720052A (en) | 1980-07-11 | 1982-02-02 | Toshiba Corp | Input data synchronizing circuit |
| GB2132042B (en) * | 1982-12-15 | 1986-09-24 | British Broadcasting Corp | Frequency and timing sources |
| WO1999013582A1 (en) * | 1997-09-09 | 1999-03-18 | Advanced Fibre Communications, Inc. | Perturbation tolerant digital phase-locked loop employing phase-frequency detector |
| WO2008152456A1 (en) * | 2007-06-14 | 2008-12-18 | Freescale Semiconductor, Inc. | Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal |
| WO2010076667A1 (en) | 2009-01-05 | 2010-07-08 | Freescale Semiconductor, Inc. | Clock glitch detection circuit |
| WO2010112969A1 (en) | 2009-03-31 | 2010-10-07 | Freescale Semiconductor, Inc. | Clock glitch detection |
-
1973
- 1973-12-20 CH CH1788973A patent/CH566089A5/xx not_active IP Right Cessation
-
1974
- 1974-11-30 DE DE19742456742 patent/DE2456742A1/de active Pending
- 1974-12-10 GB GB5339174A patent/GB1452559A/en not_active Expired
- 1974-12-13 NL NL7416281A patent/NL7416281A/xx not_active Application Discontinuation
- 1974-12-19 SE SE7415990A patent/SE398423B/xx unknown
- 1974-12-20 IT IT70707/74A patent/IT1032558B/it active
- 1974-12-20 JP JP49145849A patent/JPS50115458A/ja active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2502435A1 (fr) * | 1981-03-20 | 1982-09-24 | Victor Company Of Japan | Dispositif multiplicateur de la frequence de balayage horizontal |
| EP0089372A1 (en) * | 1981-09-28 | 1983-09-28 | Honeywell Inc. | System for preventing transient induced errors in phase locked loop |
| EP0089372A4 (en) * | 1981-09-28 | 1985-07-01 | Honeywell Inc | SYSTEM FOR ELIMINATING TRANSIENT ERRORS INDUCED IN A PHASE-LOCKED LOOP. |
| FR2526619A1 (fr) * | 1982-05-06 | 1983-11-10 | Victor Company Of Japan | Circuit de multiplication de la frequence de balayage |
| EP0645892A1 (fr) * | 1993-09-28 | 1995-03-29 | France Telecom | Dispositif d'asservissement de fréquence |
| FR2710806A1 (fr) * | 1993-09-28 | 1995-04-07 | France Telecom | Dispositif d'asservissement de fréquence. |
| WO1995018508A1 (en) * | 1993-12-29 | 1995-07-06 | Zenith Electronics Corporation | Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator |
| WO1997023049A1 (en) * | 1995-12-20 | 1997-06-26 | Italtel S.P.A. | Procedure and circuit for holding lock state in a digital pll |
Also Published As
| Publication number | Publication date |
|---|---|
| NL7416281A (nl) | 1975-06-24 |
| GB1452559A (en) | 1976-10-13 |
| SE7415990L (US06330241-20011211-M00004.png) | 1975-06-23 |
| IT1032558B (it) | 1979-06-20 |
| CH566089A5 (US06330241-20011211-M00004.png) | 1975-08-29 |
| SE398423B (sv) | 1977-12-19 |
| JPS50115458A (US06330241-20011211-M00004.png) | 1975-09-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OHJ | Non-payment of the annual fee |