DE2352331A1 - Verfahren zur herstellung einer mehrschichtigen struktur - Google Patents

Verfahren zur herstellung einer mehrschichtigen struktur

Info

Publication number
DE2352331A1
DE2352331A1 DE19732352331 DE2352331A DE2352331A1 DE 2352331 A1 DE2352331 A1 DE 2352331A1 DE 19732352331 DE19732352331 DE 19732352331 DE 2352331 A DE2352331 A DE 2352331A DE 2352331 A1 DE2352331 A1 DE 2352331A1
Authority
DE
Germany
Prior art keywords
layer
silicon
silicon dioxide
gate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19732352331
Other languages
German (de)
English (en)
Inventor
Norio Anzai
Tokio Kodaira
Yasushi Matsui
Akihiro Tomozawa
Masayasu Tsunematsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2352331A1 publication Critical patent/DE2352331A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/106Masks, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/141Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE19732352331 1972-10-27 1973-10-18 Verfahren zur herstellung einer mehrschichtigen struktur Withdrawn DE2352331A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47107222A JPS5910073B2 (ja) 1972-10-27 1972-10-27 シリコン・ゲ−トmos型半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE2352331A1 true DE2352331A1 (de) 1974-05-16

Family

ID=14453572

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732352331 Withdrawn DE2352331A1 (de) 1972-10-27 1973-10-18 Verfahren zur herstellung einer mehrschichtigen struktur

Country Status (10)

Country Link
US (1) US3906620A (US08177716-20120515-C00003.png)
JP (1) JPS5910073B2 (US08177716-20120515-C00003.png)
CA (1) CA1032659A (US08177716-20120515-C00003.png)
DE (1) DE2352331A1 (US08177716-20120515-C00003.png)
FR (1) FR2204892B1 (US08177716-20120515-C00003.png)
GB (1) GB1428713A (US08177716-20120515-C00003.png)
HK (1) HK30179A (US08177716-20120515-C00003.png)
IT (1) IT998866B (US08177716-20120515-C00003.png)
MY (1) MY7900036A (US08177716-20120515-C00003.png)
NL (1) NL179434C (US08177716-20120515-C00003.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (de) * 1975-12-03 1977-06-16 Siemens Ag Verfahren zur herstellung einer integrierten schaltung

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5293278A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for mos type semiconductor intergrated circuit
DE2858815C2 (de) * 1977-01-26 1996-01-18 Sgs Thomson Microelectronics Verfahren zur Ausbildung eines Feldeffekttransistors in einer Halbleitervorrichtung
US4553314B1 (en) * 1977-01-26 2000-04-18 Sgs Thomson Microelectronics Method for making a semiconductor device
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
US4259779A (en) * 1977-08-24 1981-04-07 Rca Corporation Method of making radiation resistant MOS transistor
US4240196A (en) * 1978-12-29 1980-12-23 Bell Telephone Laboratories, Incorporated Fabrication of two-level polysilicon devices
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US4667395A (en) * 1985-03-29 1987-05-26 International Business Machines Corporation Method for passivating an undercut in semiconductor device preparation
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
US5550069A (en) * 1990-06-23 1996-08-27 El Mos Electronik In Mos Technologie Gmbh Method for producing a PMOS transistor
US6780718B2 (en) 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
KR970003837B1 (en) * 1993-12-16 1997-03-22 Lg Semicon Co Ltd Fabrication of mosfet
JP2001291861A (ja) * 2000-04-05 2001-10-19 Nec Corp Mosトランジスタ、トランジスタ製造方法
US8435873B2 (en) 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
KR101163224B1 (ko) * 2011-02-15 2012-07-06 에스케이하이닉스 주식회사 듀얼 폴리게이트 형성방법 및 이를 이용한 반도체소자의 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB967002A (en) * 1961-05-05 1964-08-19 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices
NL131898C (US08177716-20120515-C00003.png) * 1965-03-26
NL6617141A (US08177716-20120515-C00003.png) * 1966-02-11 1967-08-14 Siemens Ag
US3764865A (en) * 1970-03-17 1973-10-09 Rca Corp Semiconductor devices having closely spaced contacts
US3798752A (en) * 1971-03-11 1974-03-26 Nippon Electric Co Method of producing a silicon gate insulated-gate field effect transistor
CA910506A (en) * 1971-06-25 1972-09-19 Bell Canada-Northern Electric Research Limited Modification of channel regions in insulated gate field effect transistors
US3775191A (en) * 1971-06-28 1973-11-27 Bell Canada Northern Electric Modification of channel regions in insulated gate field effect transistors
JPS5340762B2 (US08177716-20120515-C00003.png) * 1974-07-22 1978-10-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (de) * 1975-12-03 1977-06-16 Siemens Ag Verfahren zur herstellung einer integrierten schaltung

Also Published As

Publication number Publication date
HK30179A (en) 1979-05-18
IT998866B (it) 1976-02-20
MY7900036A (en) 1979-12-31
CA1032659A (en) 1978-06-06
NL179434B (nl) 1986-04-01
JPS5910073B2 (ja) 1984-03-06
FR2204892B1 (US08177716-20120515-C00003.png) 1976-10-01
NL7314576A (US08177716-20120515-C00003.png) 1974-05-01
GB1428713A (en) 1976-03-17
JPS4966074A (US08177716-20120515-C00003.png) 1974-06-26
FR2204892A1 (US08177716-20120515-C00003.png) 1974-05-24
US3906620A (en) 1975-09-23
NL179434C (nl) 1986-09-01

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBE

8139 Disposal/non-payment of the annual fee