DE2337555C3 - Halbleiter-Schaltungsanordnung - Google Patents

Halbleiter-Schaltungsanordnung

Info

Publication number
DE2337555C3
DE2337555C3 DE19732337555 DE2337555A DE2337555C3 DE 2337555 C3 DE2337555 C3 DE 2337555C3 DE 19732337555 DE19732337555 DE 19732337555 DE 2337555 A DE2337555 A DE 2337555A DE 2337555 C3 DE2337555 C3 DE 2337555C3
Authority
DE
Germany
Prior art keywords
clock
circuit
fet
signals
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19732337555
Other languages
German (de)
English (en)
Other versions
DE2337555B2 (de
DE2337555A1 (de
Inventor
John J. Sayville N.Y. Wunner (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Instrument Corp filed Critical General Instrument Corp
Publication of DE2337555A1 publication Critical patent/DE2337555A1/de
Publication of DE2337555B2 publication Critical patent/DE2337555B2/de
Application granted granted Critical
Publication of DE2337555C3 publication Critical patent/DE2337555C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
DE19732337555 1972-07-24 1973-07-24 Halbleiter-Schaltungsanordnung Expired DE2337555C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27430872A 1972-07-24 1972-07-24

Publications (3)

Publication Number Publication Date
DE2337555A1 DE2337555A1 (de) 1974-02-07
DE2337555B2 DE2337555B2 (de) 1977-08-11
DE2337555C3 true DE2337555C3 (de) 1978-04-06

Family

ID=23047657

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732337555 Expired DE2337555C3 (de) 1972-07-24 1973-07-24 Halbleiter-Schaltungsanordnung

Country Status (4)

Country Link
JP (1) JPS5710517B2 (enrdf_load_stackoverflow)
CA (1) CA987746A (enrdf_load_stackoverflow)
DE (1) DE2337555C3 (enrdf_load_stackoverflow)
GB (1) GB1436345A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5198932A (en) * 1975-02-26 1976-08-31 Deijitarukairono seigyohoshiki
JPS6032202Y2 (ja) * 1980-02-21 1985-09-26 株式会社明電舎 振動杭打機の制御装置
JPS56118123A (en) * 1980-02-25 1981-09-17 Matsushita Electric Ind Co Ltd Microcomputer circuit
CN112751550B (zh) * 2020-05-26 2024-04-19 上海韬润半导体有限公司 一种时钟产生电路及方法、模拟数字转换器和存储介质

Also Published As

Publication number Publication date
DE2337555B2 (de) 1977-08-11
CA987746A (en) 1976-04-20
DE2337555A1 (de) 1974-02-07
JPS5710517B2 (enrdf_load_stackoverflow) 1982-02-26
JPS4960144A (enrdf_load_stackoverflow) 1974-06-11
GB1436345A (en) 1976-05-19

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee