DE2327724A1 - Phasenstarrer oszillator - Google Patents

Phasenstarrer oszillator

Info

Publication number
DE2327724A1
DE2327724A1 DE19732327724 DE2327724A DE2327724A1 DE 2327724 A1 DE2327724 A1 DE 2327724A1 DE 19732327724 DE19732327724 DE 19732327724 DE 2327724 A DE2327724 A DE 2327724A DE 2327724 A1 DE2327724 A1 DE 2327724A1
Authority
DE
Germany
Prior art keywords
transistor
line
input
output
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19732327724
Other languages
German (de)
English (en)
Inventor
Edward R Besenfelder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of DE2327724A1 publication Critical patent/DE2327724A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DE19732327724 1972-05-30 1973-05-30 Phasenstarrer oszillator Withdrawn DE2327724A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26033572A 1972-05-30 1972-05-30

Publications (1)

Publication Number Publication Date
DE2327724A1 true DE2327724A1 (de) 1973-12-20

Family

ID=22988749

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732327724 Withdrawn DE2327724A1 (de) 1972-05-30 1973-05-30 Phasenstarrer oszillator

Country Status (5)

Country Link
US (1) US3731220A (enExample)
JP (1) JPS5750096B2 (enExample)
CA (1) CA985381A (enExample)
DE (1) DE2327724A1 (enExample)
GB (1) GB1401391A (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778793A (en) * 1972-09-11 1973-12-11 Hitachi Ltd Clocking system for magnetic memory
US3789379A (en) * 1973-02-23 1974-01-29 Honeywell Inc Compensation of reproduced signal by measuring a deviation of recorded reference signal
US3831195A (en) * 1973-07-27 1974-08-20 Burroughs Corp Multi-mode clock recovery circuit for self-clocking encoded data
US3878473A (en) * 1974-06-17 1975-04-15 Ibm Digital phase-locked loop generating signed phase values at zero crossings
US4001884A (en) * 1974-11-20 1977-01-04 Teletype Corporation Apparatus and method for recording and reproducing digital-data
US3979771A (en) * 1975-03-19 1976-09-07 Xerox Corporation Magnetic tape phase encoded data read circuit
US4017806A (en) * 1976-01-26 1977-04-12 Sperry Rand Corporation Phase locked oscillator
US4122501A (en) * 1976-12-13 1978-10-24 Sperry Rand Corporation System for recording and reading back data on a recording media
JPS5914997B2 (ja) * 1978-06-27 1984-04-06 松下電器産業株式会社 電動機の速度制御装置
US4215430A (en) * 1978-09-26 1980-07-29 Control Data Corporation Fast synchronization circuit for phase locked looped decoder
FR2454738A1 (fr) * 1979-04-18 1980-11-14 Gendrot Andre Appareil multiplex formant interface transparente et atemporelle pour l'enregistrement d'ordres et commandes
GB2138227B (en) * 1983-04-12 1987-02-04 Sony Corp Digital video tape recorder apparatus
US4542420A (en) * 1984-01-24 1985-09-17 Honeywell Inc. Manchester decoder
FR2588433B1 (fr) * 1985-10-09 1994-06-17 Bull Sa Filtre a fonction de transfert commutable et boucle a verrouillage de phase incluant ledit filtre
GB8703769D0 (en) * 1987-02-18 1987-03-25 Thorn Emi Datatech Ltd Circuit
US5946354A (en) * 1996-10-18 1999-08-31 International Business Machines Corporation Hard disk drive read channel with half speed timing
CN102126445B (zh) * 2011-01-25 2013-03-06 中国人民解放军国防科学技术大学 用于中低速磁浮列车的接地与保护方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3156874A (en) * 1960-12-16 1964-11-10 Ibm Bidirectional memory and gate synchronzing circuit for a variable frequency oscillator
US3559098A (en) * 1968-10-10 1971-01-26 Electro Optical Ind Inc Wide frequency range voltage controlled transistor relaxation oscillator
US3693112A (en) * 1971-03-12 1972-09-19 Collins Radio Co Signal controlled wide range relaxation oscillator apparatus

Also Published As

Publication number Publication date
CA985381A (en) 1976-03-09
JPS5750096B2 (enExample) 1982-10-26
GB1401391A (en) 1975-07-16
JPS4944726A (enExample) 1974-04-27
US3731220A (en) 1973-05-01

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Legal Events

Date Code Title Description
OD Request for examination
8130 Withdrawal