DE2320420A1 - Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen - Google Patents

Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen

Info

Publication number
DE2320420A1
DE2320420A1 DE2320420A DE2320420A DE2320420A1 DE 2320420 A1 DE2320420 A1 DE 2320420A1 DE 2320420 A DE2320420 A DE 2320420A DE 2320420 A DE2320420 A DE 2320420A DE 2320420 A1 DE2320420 A1 DE 2320420A1
Authority
DE
Germany
Prior art keywords
layer
connection pattern
areas
semiconductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2320420A
Other languages
German (de)
English (en)
Inventor
Ronald Roy Troutman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2320420A1 publication Critical patent/DE2320420A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0198—Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10P95/00—
    • H10W20/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
DE2320420A 1972-06-30 1973-04-21 Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen Pending DE2320420A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00267860A US3810795A (en) 1972-06-30 1972-06-30 Method for making self-aligning structure for charge-coupled and bucket brigade devices

Publications (1)

Publication Number Publication Date
DE2320420A1 true DE2320420A1 (de) 1974-01-17

Family

ID=23020423

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2320420A Pending DE2320420A1 (de) 1972-06-30 1973-04-21 Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen

Country Status (5)

Country Link
US (1) US3810795A (enExample)
JP (1) JPS5637707B2 (enExample)
DE (1) DE2320420A1 (enExample)
FR (1) FR2191269B1 (enExample)
GB (1) GB1425864A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967306A (en) * 1973-08-01 1976-06-29 Trw Inc. Asymmetrical well charge coupled device
US3927468A (en) * 1973-12-28 1975-12-23 Fairchild Camera Instr Co Self aligned CCD element fabrication method therefor
US3911560A (en) * 1974-02-25 1975-10-14 Fairchild Camera Instr Co Method for manufacturing a semiconductor device having self-aligned implanted barriers with narrow gaps between electrodes
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS5910581B2 (ja) * 1977-12-01 1984-03-09 富士通株式会社 半導体装置の製造方法
US4933297A (en) * 1989-10-12 1990-06-12 At&T Bell Laboratories Method for etching windows having different depths
US7846760B2 (en) * 2006-05-31 2010-12-07 Kenet, Inc. Doped plug for CCD gaps

Also Published As

Publication number Publication date
JPS4959581A (enExample) 1974-06-10
GB1425864A (en) 1976-02-18
US3810795A (en) 1974-05-14
FR2191269A1 (enExample) 1974-02-01
FR2191269B1 (enExample) 1977-09-09
JPS5637707B2 (enExample) 1981-09-02

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