DE2318912A1 - Integrierte halbleiteranordnung - Google Patents

Integrierte halbleiteranordnung

Info

Publication number
DE2318912A1
DE2318912A1 DE2318912A DE2318912A DE2318912A1 DE 2318912 A1 DE2318912 A1 DE 2318912A1 DE 2318912 A DE2318912 A DE 2318912A DE 2318912 A DE2318912 A DE 2318912A DE 2318912 A1 DE2318912 A1 DE 2318912A1
Authority
DE
Germany
Prior art keywords
layer
zones
epitaxial layer
isolation
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2318912A
Other languages
German (de)
English (en)
Inventor
Shakir Ahmed Abbas
Chi Shih Chang
Jun Leo Boyes Freeman
Ronald William Knepper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2318912A1 publication Critical patent/DE2318912A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

  • Semiconductor Memories (AREA)
DE2318912A 1972-06-30 1973-04-14 Integrierte halbleiteranordnung Ceased DE2318912A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26777172A 1972-06-30 1972-06-30

Publications (1)

Publication Number Publication Date
DE2318912A1 true DE2318912A1 (de) 1974-01-17

Family

ID=23020055

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2318912A Ceased DE2318912A1 (de) 1972-06-30 1973-04-14 Integrierte halbleiteranordnung

Country Status (6)

Country Link
JP (1) JPS528229B2 (enExample)
CA (1) CA1005925A (enExample)
DE (1) DE2318912A1 (enExample)
FR (1) FR2191270B1 (enExample)
GB (1) GB1422586A (enExample)
IT (1) IT987426B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (de) * 1975-12-03 1977-06-16 Siemens Ag Verfahren zur herstellung einer integrierten schaltung
DE3508996A1 (de) * 1984-04-17 1985-10-24 Mitsubishi Denki K.K., Tokio/Tokyo Integrierte halbleiterschaltungseinrichtung

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2720533A1 (de) * 1977-05-06 1978-11-09 Siemens Ag Monolithisch integrierte schaltungsanordnung mit ein-transistor- speicherelementen
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58100441A (ja) * 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
JPS58212165A (ja) * 1983-05-23 1983-12-09 Nec Corp 半導体装置
JP2003124514A (ja) * 2001-10-17 2003-04-25 Sony Corp 半導体発光素子及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
FR2079612A5 (enExample) * 1970-02-06 1971-11-12 Radiotechnique Compelec
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3859717A (en) * 1970-12-21 1975-01-14 Rockwell International Corp Method of manufacturing control electrodes for charge coupled circuits and the like
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (de) * 1975-12-03 1977-06-16 Siemens Ag Verfahren zur herstellung einer integrierten schaltung
DE3508996A1 (de) * 1984-04-17 1985-10-24 Mitsubishi Denki K.K., Tokio/Tokyo Integrierte halbleiterschaltungseinrichtung
US5049959A (en) * 1984-04-17 1991-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS4945688A (enExample) 1974-05-01
GB1422586A (en) 1976-01-28
FR2191270A1 (enExample) 1974-02-01
JPS528229B2 (enExample) 1977-03-08
FR2191270B1 (enExample) 1977-07-29
IT987426B (it) 1975-02-20
CA1005925A (en) 1977-02-22

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Legal Events

Date Code Title Description
OD Request for examination
8131 Rejection