CA1005925A - Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming - Google Patents

Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming

Info

Publication number
CA1005925A
CA1005925A CA173,051A CA173051A CA1005925A CA 1005925 A CA1005925 A CA 1005925A CA 173051 A CA173051 A CA 173051A CA 1005925 A CA1005925 A CA 1005925A
Authority
CA
Canada
Prior art keywords
forming
semiconductor device
electrically insulating
sensitive devices
insulating barriers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA173,051A
Other versions
CA173051S (en
Inventor
Shakir A. Abbas
Chi S. Chang
Ronald W. Knepper
Leo B. Freeman (Jr.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1005925A publication Critical patent/CA1005925A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
CA173,051A 1972-06-30 1973-06-04 Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming Expired CA1005925A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26777172A 1972-06-30 1972-06-30

Publications (1)

Publication Number Publication Date
CA1005925A true CA1005925A (en) 1977-02-22

Family

ID=23020055

Family Applications (1)

Application Number Title Priority Date Filing Date
CA173,051A Expired CA1005925A (en) 1972-06-30 1973-06-04 Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming

Country Status (6)

Country Link
JP (1) JPS528229B2 (en)
CA (1) CA1005925A (en)
DE (1) DE2318912A1 (en)
FR (1) FR2191270B1 (en)
GB (1) GB1422586A (en)
IT (1) IT987426B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (en) * 1975-12-03 1977-06-16 Siemens Ag Integrated circuit prodn. with FET in silicon substrate - with polycrystalline silicon gate electrode and planar insulating oxide film
DE2720533A1 (en) * 1977-05-06 1978-11-09 Siemens Ag MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT WITH SINGLE TRANSISTOR STORAGE ELEMENTS
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58100441A (en) * 1981-12-10 1983-06-15 Toshiba Corp Manufacture of semiconductor device
JPS58212165A (en) * 1983-05-23 1983-12-09 Nec Corp Semiconductor device
JPH0616549B2 (en) * 1984-04-17 1994-03-02 三菱電機株式会社 Semiconductor integrated circuit device
JP2003124514A (en) * 2001-10-17 2003-04-25 Sony Corp Semiconductor light emitting element and its manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (en) * 1966-10-05 1977-05-16 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE PROVIDED WITH AN OXIDE LAYER AND SEMI-CONDUCTOR DEVICE MANUFACTURED ACCORDING TO THE PROCEDURE.
FR2080849A6 (en) * 1970-02-06 1971-11-26 Radiotechnique Compelec
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3859717A (en) * 1970-12-21 1975-01-14 Rockwell International Corp Method of manufacturing control electrodes for charge coupled circuits and the like
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions

Also Published As

Publication number Publication date
FR2191270A1 (en) 1974-02-01
JPS4945688A (en) 1974-05-01
IT987426B (en) 1975-02-20
FR2191270B1 (en) 1977-07-29
GB1422586A (en) 1976-01-28
JPS528229B2 (en) 1977-03-08
DE2318912A1 (en) 1974-01-17

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