DE2316208B2 - Verfahren zur herstellung einer integrierten mos-schaltung - Google Patents

Verfahren zur herstellung einer integrierten mos-schaltung

Info

Publication number
DE2316208B2
DE2316208B2 DE19732316208 DE2316208A DE2316208B2 DE 2316208 B2 DE2316208 B2 DE 2316208B2 DE 19732316208 DE19732316208 DE 19732316208 DE 2316208 A DE2316208 A DE 2316208A DE 2316208 B2 DE2316208 B2 DE 2316208B2
Authority
DE
Germany
Prior art keywords
silicon wafer
oxide layer
field effect
insulating layer
effect transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19732316208
Other languages
German (de)
English (en)
Other versions
DE2316208A1 (de
Inventor
Farajollah San Jose Calif. Kashkooli (V.StA.)
Original Assignee
Signetics Corp., Sunnyvale, Calif. (V.St.A.)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp., Sunnyvale, Calif. (V.St.A.) filed Critical Signetics Corp., Sunnyvale, Calif. (V.St.A.)
Publication of DE2316208A1 publication Critical patent/DE2316208A1/de
Publication of DE2316208B2 publication Critical patent/DE2316208B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
DE19732316208 1972-04-24 1973-03-31 Verfahren zur herstellung einer integrierten mos-schaltung Withdrawn DE2316208B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US24691872A 1972-04-24 1972-04-24

Publications (2)

Publication Number Publication Date
DE2316208A1 DE2316208A1 (de) 1973-11-08
DE2316208B2 true DE2316208B2 (de) 1977-04-28

Family

ID=22932770

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732316208 Withdrawn DE2316208B2 (de) 1972-04-24 1973-03-31 Verfahren zur herstellung einer integrierten mos-schaltung

Country Status (8)

Country Link
US (1) US3787251A (OSRAM)
JP (1) JPS5132550B2 (OSRAM)
CA (1) CA977461A (OSRAM)
DE (1) DE2316208B2 (OSRAM)
FR (1) FR2181960B1 (OSRAM)
GB (1) GB1385160A (OSRAM)
IT (1) IT981799B (OSRAM)
NL (1) NL7304322A (OSRAM)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE375881B (OSRAM) * 1972-11-17 1975-04-28 Asea Ab
JPS5534582B2 (OSRAM) * 1974-06-24 1980-09-08
US4056825A (en) * 1975-06-30 1977-11-01 International Business Machines Corporation FET device with reduced gate overlap capacitance of source/drain and method of manufacture
US4048350A (en) * 1975-09-19 1977-09-13 International Business Machines Corporation Semiconductor device having reduced surface leakage and methods of manufacture
US5043293A (en) * 1984-05-03 1991-08-27 Texas Instruments Incorporated Dual oxide channel stop for semiconductor devices
JPH01185936A (ja) * 1988-01-21 1989-07-25 Fujitsu Ltd 半導体装置
US5387530A (en) * 1993-06-29 1995-02-07 Digital Equipment Corporation Threshold optimization for soi transistors through use of negative charge in the gate oxide
US5407850A (en) * 1993-06-29 1995-04-18 Digital Equipment Corporation SOI transistor threshold optimization by use of gate oxide having positive charge
US6629959B2 (en) 1996-02-27 2003-10-07 Injectimed, Inc. Needle tip guard for percutaneous entry needles
JP2001502191A (ja) 1996-02-27 2001-02-20 インジェクタイムド・インコーポレーテッド 皮下注射針の針先ガード
JP2000174135A (ja) * 1998-12-07 2000-06-23 Mitsubishi Electric Corp 半導体装置及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3345275A (en) * 1964-04-28 1967-10-03 Westinghouse Electric Corp Electrolyte and diffusion process
US3386163A (en) * 1964-08-26 1968-06-04 Ibm Method for fabricating insulated-gate field effect transistor
US3402081A (en) * 1965-06-30 1968-09-17 Ibm Method for controlling the electrical characteristics of a semiconductor surface and product produced thereby
US3447238A (en) * 1965-08-09 1969-06-03 Raytheon Co Method of making a field effect transistor by diffusion,coating with an oxide and placing a metal layer on the oxide
US3560280A (en) * 1965-11-17 1971-02-02 Hitachi Ltd Method of selective removal of oxide coatings in the manufacture of semiconductor devices
US3547717A (en) * 1968-04-29 1970-12-15 Sprague Electric Co Radiation resistant semiconductive device

Also Published As

Publication number Publication date
DE2316208A1 (de) 1973-11-08
GB1385160A (en) 1975-02-26
FR2181960A1 (OSRAM) 1973-12-07
JPS4955286A (OSRAM) 1974-05-29
FR2181960B1 (OSRAM) 1977-09-02
IT981799B (it) 1974-10-10
NL7304322A (OSRAM) 1973-10-26
CA977461A (en) 1975-11-04
US3787251A (en) 1974-01-22
JPS5132550B2 (OSRAM) 1976-09-13

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