DE2149566C3 - Verfahren zur Herstellung einer integrierten Halbleiterschaltung, deren Schaltungselement durch dielektrisches Material voneinander isoliert sind - Google Patents

Verfahren zur Herstellung einer integrierten Halbleiterschaltung, deren Schaltungselement durch dielektrisches Material voneinander isoliert sind

Info

Publication number
DE2149566C3
DE2149566C3 DE2149566A DE2149566A DE2149566C3 DE 2149566 C3 DE2149566 C3 DE 2149566C3 DE 2149566 A DE2149566 A DE 2149566A DE 2149566 A DE2149566 A DE 2149566A DE 2149566 C3 DE2149566 C3 DE 2149566C3
Authority
DE
Germany
Prior art keywords
etching
silicon
silicon layer
etched
etchant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2149566A
Other languages
German (de)
English (en)
Other versions
DE2149566A1 (de
DE2149566B2 (de
Inventor
Taizo Kanagawa Ohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP8658670A external-priority patent/JPS4945035B1/ja
Priority claimed from JP4925071A external-priority patent/JPS5521461B1/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE2149566A1 publication Critical patent/DE2149566A1/de
Publication of DE2149566B2 publication Critical patent/DE2149566B2/de
Application granted granted Critical
Publication of DE2149566C3 publication Critical patent/DE2149566C3/de
Expired legal-status Critical Current

Links

Classifications

    • H10P50/642—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
DE2149566A 1970-10-05 1971-10-05 Verfahren zur Herstellung einer integrierten Halbleiterschaltung, deren Schaltungselement durch dielektrisches Material voneinander isoliert sind Expired DE2149566C3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8658670A JPS4945035B1 (OSRAM) 1970-10-05 1970-10-05
JP4925071A JPS5521461B1 (OSRAM) 1971-07-06 1971-07-06

Publications (3)

Publication Number Publication Date
DE2149566A1 DE2149566A1 (de) 1972-04-06
DE2149566B2 DE2149566B2 (de) 1980-11-27
DE2149566C3 true DE2149566C3 (de) 1981-07-23

Family

ID=26389625

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2149566A Expired DE2149566C3 (de) 1970-10-05 1971-10-05 Verfahren zur Herstellung einer integrierten Halbleiterschaltung, deren Schaltungselement durch dielektrisches Material voneinander isoliert sind

Country Status (6)

Country Link
US (1) US3756877A (OSRAM)
CA (1) CA924026A (OSRAM)
DE (1) DE2149566C3 (OSRAM)
FR (1) FR2110235B1 (OSRAM)
GB (1) GB1345752A (OSRAM)
NL (1) NL169802C (OSRAM)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2294549A1 (fr) * 1974-12-09 1976-07-09 Radiotechnique Compelec Procede de realisation de dispositifs optoelectroniques
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
JPS5215262A (en) * 1975-07-28 1977-02-04 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacturing method
DE69232347T2 (de) * 1991-09-27 2002-07-11 Canon K.K., Tokio/Tokyo Verfahren zur Behandlung eines Substrats aus Silizium
EP0536790B1 (en) * 1991-10-11 2004-03-03 Canon Kabushiki Kaisha Method for producing semiconductor articles
US5843322A (en) * 1996-12-23 1998-12-01 Memc Electronic Materials, Inc. Process for etching N, P, N+ and P+ type slugs and wafers
CN111019659B (zh) * 2019-12-06 2021-06-08 湖北兴福电子材料有限公司 一种选择性硅蚀刻液

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372063A (en) * 1964-12-22 1968-03-05 Hitachi Ltd Method for manufacturing at least one electrically isolated region of a semiconductive material
FR1483068A (fr) * 1965-05-10 1967-06-02 Ibm Montage de dispositif à semi-conducteur et procédé de fabrication

Also Published As

Publication number Publication date
CA924026A (en) 1973-04-03
FR2110235B1 (OSRAM) 1977-03-18
NL7113629A (OSRAM) 1972-04-07
US3756877A (en) 1973-09-04
FR2110235A1 (OSRAM) 1972-06-02
NL169802C (nl) 1982-08-16
DE2149566A1 (de) 1972-04-06
GB1345752A (en) 1974-02-06
NL169802B (nl) 1982-03-16
DE2149566B2 (de) 1980-11-27

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8320 Willingness to grant licences declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP