DE2139753C3 - Rechenwerk für die Addition von zwei seriell vorliegenden Dezimalzahlen - Google Patents
Rechenwerk für die Addition von zwei seriell vorliegenden DezimalzahlenInfo
- Publication number
- DE2139753C3 DE2139753C3 DE19712139753 DE2139753A DE2139753C3 DE 2139753 C3 DE2139753 C3 DE 2139753C3 DE 19712139753 DE19712139753 DE 19712139753 DE 2139753 A DE2139753 A DE 2139753A DE 2139753 C3 DE2139753 C3 DE 2139753C3
- Authority
- DE
- Germany
- Prior art keywords
- adder
- decimal
- cycle
- arithmetic unit
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
- G06F2207/4919—Using excess-3 code, i.e. natural BCD + offset of 3, rendering the code symmetrical within the series of 16 possible 4 bit values
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Error Detection And Correction (AREA)
- Complex Calculations (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712139753 DE2139753C3 (de) | 1971-08-07 | 1971-08-07 | Rechenwerk für die Addition von zwei seriell vorliegenden Dezimalzahlen |
| GB3566672A GB1371552A (en) | 1971-08-07 | 1972-07-31 | Arithmetic unit for the addition of two serially-present decimal numbers |
| FR7227793A FR2149824A5 (Direct) | 1971-08-07 | 1972-08-02 | |
| IT2788172A IT963732B (it) | 1971-08-07 | 1972-08-04 | Calcolatore per l addizione di due numeri decimali rappresentati in serie |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712139753 DE2139753C3 (de) | 1971-08-07 | 1971-08-07 | Rechenwerk für die Addition von zwei seriell vorliegenden Dezimalzahlen |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| DE2139753A1 DE2139753A1 (de) | 1973-02-22 |
| DE2139753B2 DE2139753B2 (de) | 1973-07-19 |
| DE2139753C3 true DE2139753C3 (de) | 1974-02-21 |
Family
ID=5816179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19712139753 Expired DE2139753C3 (de) | 1971-08-07 | 1971-08-07 | Rechenwerk für die Addition von zwei seriell vorliegenden Dezimalzahlen |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE2139753C3 (Direct) |
| FR (1) | FR2149824A5 (Direct) |
| GB (1) | GB1371552A (Direct) |
| IT (1) | IT963732B (Direct) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137381A (ja) * | 1982-02-10 | 1983-08-15 | Sony Corp | デイジタルカラ−エンコ−ダ |
-
1971
- 1971-08-07 DE DE19712139753 patent/DE2139753C3/de not_active Expired
-
1972
- 1972-07-31 GB GB3566672A patent/GB1371552A/en not_active Expired
- 1972-08-02 FR FR7227793A patent/FR2149824A5/fr not_active Expired
- 1972-08-04 IT IT2788172A patent/IT963732B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| IT963732B (it) | 1974-01-21 |
| GB1371552A (en) | 1974-10-23 |
| DE2139753B2 (de) | 1973-07-19 |
| FR2149824A5 (Direct) | 1973-03-30 |
| DE2139753A1 (de) | 1973-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE2524046C2 (de) | Elektronische Datenverarbeitungsanlage | |
| DE2712224A1 (de) | Datenverarbeitungsanlage | |
| DE2023354A1 (de) | Programmierbare Einheit und Verfahren zum Betreiben einer programmierbaren Einheit | |
| DE1236834B (de) | Rechengeraet | |
| DE2626432A1 (de) | Arithmetische einheit fuer automatische rechengeraete | |
| DE1549508C3 (de) | Anordnung zur Übertragsberechnung mit kurzer Signallaufzeit | |
| DE3303269C2 (Direct) | ||
| DE2442535A1 (de) | Funktionswaehleinrichtung fuer elektronischen rechner, insbesondere taschenrechner | |
| DE2139753C3 (de) | Rechenwerk für die Addition von zwei seriell vorliegenden Dezimalzahlen | |
| DE1524117B1 (de) | Datenverarbeitungsanlage mit Umlaufregistern | |
| DE1499227C3 (de) | Schaltungsanordnung für arithmetische und logische Grundoperationen | |
| DE1965830C3 (de) | Vorrichtung zur Eingabe einer Dezimalzahl mit wählbarer Kommastelle in eine Rechenmaschine | |
| DE2712582C2 (de) | DDA-Rechner (Digital-Differential-Analysator) | |
| DE1549485C3 (de) | Anordnung zur Division binärer Operanden ohne Rückstellung des Restes | |
| DE1103646B (de) | Inkrement-Rechenmaschine | |
| DE1549449A1 (de) | Einrichtung zur Verarbeitung von Gleitkommazahlen | |
| DE1915493C3 (de) | Schaltung für Multiplikation nach dem Prinzip der fortgesetzten, stellenversetzten Addition | |
| DE3513916C2 (de) | Pseudo-Zufallsgenerator | |
| DE1803607C3 (de) | Schaltungsanordnung zur Umsetzung einer Dualzahl in eine im BCD Kode ver schlüsselte Dezimalzahl | |
| DE1817635C3 (de) | Verfahren und Einrichtung zum Betrieb einert tastengesteuerten Rechenmaschine | |
| DE1524146C (de) | Divisionseinrichtung | |
| DE2853540A1 (de) | Rechenelement nach dem dda-prinzip | |
| DE2136600C3 (de) | Anordnung zur automatischen Prozentrechnung | |
| DE1524117C (de) | Datenverarbeitungsanlage mit Umlaufregistern | |
| DE1157009B (de) | Rechenwerk einer digitalen Rechenmaschine |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C3 | Grant after two publication steps (3rd publication) |