DE2100224C3 - Maskierungs- und Metallisierungsverfahren bei der Herstellung von Halbleiterzonen - Google Patents

Maskierungs- und Metallisierungsverfahren bei der Herstellung von Halbleiterzonen

Info

Publication number
DE2100224C3
DE2100224C3 DE2100224A DE2100224A DE2100224C3 DE 2100224 C3 DE2100224 C3 DE 2100224C3 DE 2100224 A DE2100224 A DE 2100224A DE 2100224 A DE2100224 A DE 2100224A DE 2100224 C3 DE2100224 C3 DE 2100224C3
Authority
DE
Germany
Prior art keywords
layer
semiconductor
aluminum
metal layer
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2100224A
Other languages
German (de)
English (en)
Other versions
DE2100224B2 (de
DE2100224A1 (de
Inventor
Vir Abhimanyu Hopewell Junction Dhaka
Andrew Fabian Poughkeepsie Kozik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2100224A1 publication Critical patent/DE2100224A1/de
Publication of DE2100224B2 publication Critical patent/DE2100224B2/de
Application granted granted Critical
Publication of DE2100224C3 publication Critical patent/DE2100224C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H10P95/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H10P14/6314—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
DE2100224A 1970-01-22 1971-01-05 Maskierungs- und Metallisierungsverfahren bei der Herstellung von Halbleiterzonen Expired DE2100224C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US496670A 1970-01-22 1970-01-22

Publications (3)

Publication Number Publication Date
DE2100224A1 DE2100224A1 (de) 1971-07-29
DE2100224B2 DE2100224B2 (de) 1978-09-28
DE2100224C3 true DE2100224C3 (de) 1979-05-31

Family

ID=21713436

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2100224A Expired DE2100224C3 (de) 1970-01-22 1971-01-05 Maskierungs- und Metallisierungsverfahren bei der Herstellung von Halbleiterzonen

Country Status (5)

Country Link
US (1) US3681147A (enExample)
JP (1) JPS5435075B1 (enExample)
DE (1) DE2100224C3 (enExample)
FR (1) FR2077263B1 (enExample)
GB (1) GB1270227A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3882000A (en) * 1974-05-09 1975-05-06 Bell Telephone Labor Inc Formation of composite oxides on III-V semiconductors
US4038107B1 (en) * 1975-12-03 1995-04-18 Samsung Semiconductor Tele Method for making transistor structures
JPS5676539A (en) * 1979-11-28 1981-06-24 Sumitomo Electric Ind Ltd Formation of insulating film on semiconductor substrate
US4517734A (en) * 1982-05-12 1985-05-21 Eastman Kodak Company Method of passivating aluminum interconnects of non-hermetically sealed integrated circuit semiconductor devices
NL8303268A (nl) * 1983-09-23 1985-04-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting en halfgeleiderinrichting vervaardigd door toepassing van een dergelijke werkwijze.
EP0221351B1 (de) * 1985-10-22 1991-09-25 Siemens Aktiengesellschaft Integrierte Halbleiterschaltung mit einem elektrisch leitenden Flächenelement
DE10332725A1 (de) * 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Verfahren zur selbstjustierenden Verkleinerung von Strukturen
TWI683351B (zh) * 2017-12-14 2020-01-21 新唐科技股份有限公司 半導體裝置及其形成方法

Also Published As

Publication number Publication date
US3681147A (en) 1972-08-01
DE2100224B2 (de) 1978-09-28
FR2077263B1 (enExample) 1975-02-21
JPS5435075B1 (enExample) 1979-10-31
FR2077263A1 (enExample) 1971-10-22
GB1270227A (en) 1972-04-12
DE2100224A1 (de) 1971-07-29

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee