DE19983426T1 - Herstellung einer Halbleitervorrichtung mit getrennten Schaltungselementausbildungsschichten unterschiedlicher Dicke - Google Patents

Herstellung einer Halbleitervorrichtung mit getrennten Schaltungselementausbildungsschichten unterschiedlicher Dicke

Info

Publication number
DE19983426T1
DE19983426T1 DE19983426T DE19983426T DE19983426T1 DE 19983426 T1 DE19983426 T1 DE 19983426T1 DE 19983426 T DE19983426 T DE 19983426T DE 19983426 T DE19983426 T DE 19983426T DE 19983426 T1 DE19983426 T1 DE 19983426T1
Authority
DE
Germany
Prior art keywords
manufacture
semiconductor device
circuit element
different thickness
element formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983426T
Other languages
English (en)
Other versions
DE19983426B4 (de
Inventor
Michihiro Kawano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Microsystems Co Ltd
Original Assignee
Asahi Kasei Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Microsystems Co Ltd filed Critical Asahi Kasei Microsystems Co Ltd
Publication of DE19983426T1 publication Critical patent/DE19983426T1/de
Application granted granted Critical
Publication of DE19983426B4 publication Critical patent/DE19983426B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE19983426T 1999-06-03 1999-06-03 Verfahren zum Herstellen einer Halbleitervorrichtung mit getrennten Schaltungselementausbildungsschichten unterschiedlicher Dicken Expired - Fee Related DE19983426B4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/002981 WO2000075981A1 (fr) 1999-06-03 1999-06-03 Procede de fabrication d'un dispositif a semi-conducteurs

Publications (2)

Publication Number Publication Date
DE19983426T1 true DE19983426T1 (de) 2001-06-13
DE19983426B4 DE19983426B4 (de) 2005-09-22

Family

ID=14235890

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983426T Expired - Fee Related DE19983426B4 (de) 1999-06-03 1999-06-03 Verfahren zum Herstellen einer Halbleitervorrichtung mit getrennten Schaltungselementausbildungsschichten unterschiedlicher Dicken

Country Status (4)

Country Link
US (1) US6387741B1 (de)
KR (1) KR100383702B1 (de)
DE (1) DE19983426B4 (de)
WO (1) WO2000075981A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355580B1 (en) 1998-09-03 2002-03-12 Micron Technology, Inc. Ion-assisted oxidation methods and the resulting structures
US6846727B2 (en) * 2001-05-21 2005-01-25 International Business Machines Corporation Patterned SOI by oxygen implantation and annealing
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
JP2004152962A (ja) * 2002-10-30 2004-05-27 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR100489802B1 (ko) * 2002-12-18 2005-05-16 한국전자통신연구원 고전압 및 저전압 소자의 구조와 그 제조 방법
FR2872958B1 (fr) * 2004-07-12 2008-05-02 Commissariat Energie Atomique Procede de fabrication d'un film mince structure et film mince obtenu par un tel procede

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5461488A (en) 1977-10-26 1979-05-17 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS57196543A (en) 1981-05-27 1982-12-02 Toshiba Corp Manufacture of semiconductor device
JPS61222137A (ja) * 1985-03-06 1986-10-02 Sharp Corp チップ識別用凹凸パターン形成方法
JPS63177564A (ja) 1987-01-19 1988-07-21 Fujitsu Ltd 半導体装置
US5212397A (en) * 1990-08-13 1993-05-18 Motorola, Inc. BiCMOS device having an SOI substrate and process for making the same
DE69223009T2 (de) * 1991-08-02 1998-04-02 Canon Kk Flüssigkristall-Anzeigeeinheit
US5463238A (en) * 1992-02-25 1995-10-31 Seiko Instruments Inc. CMOS structure with parasitic channel prevention
TW214603B (en) * 1992-05-13 1993-10-11 Seiko Electron Co Ltd Semiconductor device
JPH07106579A (ja) * 1993-10-08 1995-04-21 Hitachi Ltd 半導体装置とその製造方法
JP3265569B2 (ja) * 1998-04-15 2002-03-11 日本電気株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR20010106428A (ko) 2001-11-29
US6387741B1 (en) 2002-05-14
DE19983426B4 (de) 2005-09-22
WO2000075981A1 (fr) 2000-12-14
KR100383702B1 (ko) 2003-05-16

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8607 Notification of search results after publication
8128 New person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 M?NCHEN

8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee