DE69923126D1 - Integrierte Schaltung mit mehreren Prozessorkernen - Google Patents

Integrierte Schaltung mit mehreren Prozessorkernen

Info

Publication number
DE69923126D1
DE69923126D1 DE69923126T DE69923126T DE69923126D1 DE 69923126 D1 DE69923126 D1 DE 69923126D1 DE 69923126 T DE69923126 T DE 69923126T DE 69923126 T DE69923126 T DE 69923126T DE 69923126 D1 DE69923126 D1 DE 69923126D1
Authority
DE
Germany
Prior art keywords
integrated circuit
processor cores
multiple processor
cores
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69923126T
Other languages
English (en)
Inventor
Robert Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69923126D1 publication Critical patent/DE69923126D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69923126T 1998-08-21 1999-08-04 Integrierte Schaltung mit mehreren Prozessorkernen Expired - Lifetime DE69923126D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9818377.5A GB9818377D0 (en) 1998-08-21 1998-08-21 An integrated circuit with multiple processing cores

Publications (1)

Publication Number Publication Date
DE69923126D1 true DE69923126D1 (de) 2005-02-17

Family

ID=10837704

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69923126T Expired - Lifetime DE69923126D1 (de) 1998-08-21 1999-08-04 Integrierte Schaltung mit mehreren Prozessorkernen

Country Status (4)

Country Link
US (1) US6675284B1 (de)
EP (1) EP0982595B1 (de)
DE (1) DE69923126D1 (de)
GB (1) GB9818377D0 (de)

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US20090245257A1 (en) * 2008-04-01 2009-10-01 International Business Machines Corporation Network On Chip
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Also Published As

Publication number Publication date
EP0982595A1 (de) 2000-03-01
GB9818377D0 (en) 1998-10-21
EP0982595B1 (de) 2005-01-12
US6675284B1 (en) 2004-01-06

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Legal Events

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8332 No legal effect for de