DE602004026401D1 - Verfahren zur Implementierung eines Abtastratenumsetzers mit rationalem Umsetzungsfaktor (FSRC) und entsprechende Architektur - Google Patents

Verfahren zur Implementierung eines Abtastratenumsetzers mit rationalem Umsetzungsfaktor (FSRC) und entsprechende Architektur

Info

Publication number
DE602004026401D1
DE602004026401D1 DE602004026401T DE602004026401T DE602004026401D1 DE 602004026401 D1 DE602004026401 D1 DE 602004026401D1 DE 602004026401 T DE602004026401 T DE 602004026401T DE 602004026401 T DE602004026401 T DE 602004026401T DE 602004026401 D1 DE602004026401 D1 DE 602004026401D1
Authority
DE
Germany
Prior art keywords
fsrc
implementing
sample rate
conversion factor
rate converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004026401T
Other languages
English (en)
Inventor
Vito Antonio Avantaggiati
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Accent SpA
Original Assignee
Accent SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Accent SpA filed Critical Accent SpA
Publication of DE602004026401D1 publication Critical patent/DE602004026401D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0685—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being rational

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Television Systems (AREA)
  • Analogue/Digital Conversion (AREA)
DE602004026401T 2004-02-24 2004-02-24 Verfahren zur Implementierung eines Abtastratenumsetzers mit rationalem Umsetzungsfaktor (FSRC) und entsprechende Architektur Expired - Lifetime DE602004026401D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04425111A EP1569336B1 (de) 2004-02-24 2004-02-24 Verfahren zur Implementierung eines Abtastratenumsetzers mit rationalem Umsetzungsfaktor (FSRC) und entsprechende Architektur

Publications (1)

Publication Number Publication Date
DE602004026401D1 true DE602004026401D1 (de) 2010-05-20

Family

ID=34746209

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004026401T Expired - Lifetime DE602004026401D1 (de) 2004-02-24 2004-02-24 Verfahren zur Implementierung eines Abtastratenumsetzers mit rationalem Umsetzungsfaktor (FSRC) und entsprechende Architektur

Country Status (3)

Country Link
US (1) US7126505B2 (de)
EP (1) EP1569336B1 (de)
DE (1) DE602004026401D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7245237B2 (en) * 2002-09-17 2007-07-17 Intel Corporation Digital sampling rate conversion using a poly-phase filter and a polynomial interpolator
US7180435B2 (en) * 2004-02-02 2007-02-20 Broadcom Corporation Low-complexity sampling rate conversion method and apparatus for audio processing
US7508327B2 (en) * 2006-06-14 2009-03-24 Qualcomm Incorporated Integer representation of relative timing between desired output samples and corresponding input samples
SI22825A (sl) * 2008-05-27 2009-12-31 Instrumentation Technologies D.O.O. Postopek kompenzacije nelinearnih popačenj visokofrekvenčnih signalov in naprava za izvedbo postopka
US8467891B2 (en) * 2009-01-21 2013-06-18 Utc Fire & Security Americas Corporation, Inc. Method and system for efficient optimization of audio sampling rate conversion
US8217812B2 (en) * 2010-03-11 2012-07-10 Qualcomm Incorporated Adjustable sampling rate converter
US8542786B2 (en) * 2010-08-04 2013-09-24 Evertz Microsystems Ltd. Multi-channel sample rate converter
KR20150012146A (ko) * 2012-07-24 2015-02-03 삼성전자주식회사 오디오 데이터를 처리하기 위한 방법 및 장치
US9052991B2 (en) * 2012-11-27 2015-06-09 Qualcomm Incorporated System and method for audio sample rate conversion

Family Cites Families (23)

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Publication number Priority date Publication date Assignee Title
US4308598A (en) * 1979-07-09 1981-12-29 The Anaconda Company Simplified roll along switching
JPS56116147A (en) * 1980-02-20 1981-09-11 Hitachi Ltd Digital semiconductor integrated circuit and digital control system using it
JPS60237527A (ja) * 1984-05-11 1985-11-26 Mitsubishi Electric Corp Ａ−ｄ変換装置
GB2188806B (en) * 1986-04-05 1989-11-01 Burr Brown Ltd Method and apparatus for improved interface unit between analog input signals and a digital signal bus
GB2198897A (en) * 1986-12-18 1988-06-22 Burr Brown Ltd Analog input system
JP2574909B2 (ja) * 1989-12-11 1997-01-22 三菱電機株式会社 マイクロコンピュータ
JPH04160438A (ja) * 1990-10-23 1992-06-03 Mitsubishi Electric Corp 半導体装置
GB9205614D0 (en) * 1992-03-14 1992-04-29 Innovision Ltd Sample rate converter suitable for converting between digital video formats
DE69316559T2 (de) * 1992-12-03 1998-09-10 Advanced Micro Devices Inc Servoregelkreissteuerung
US5581794A (en) * 1992-12-18 1996-12-03 Amdahl Corporation Apparatus for generating a channel time-out signal after 16.38 milliseconds
DE69424754T2 (de) * 1993-12-08 2001-01-25 Nokia Mobile Phones Ltd., Salo Verfahren zur Umsetzung der Abtastfrequenz
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
JPH10143350A (ja) * 1996-11-06 1998-05-29 Nec Corp 先入れ先出しメモリ制御システム
US5907295A (en) * 1997-08-04 1999-05-25 Neomagic Corp. Audio sample-rate conversion using a linear-interpolation stage with a multi-tap low-pass filter requiring reduced coefficient storage
US6275836B1 (en) * 1998-06-12 2001-08-14 Oak Technology, Inc. Interpolation filter and method for switching between integer and fractional interpolation rates
US6480913B1 (en) * 1998-07-17 2002-11-12 3Dlabs Inc. Led. Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter
GB9818377D0 (en) * 1998-08-21 1998-10-21 Sgs Thomson Microelectronics An integrated circuit with multiple processing cores
US6362755B1 (en) * 2000-04-18 2002-03-26 Sigmatel, Inc. Method and apparatus for sample rate conversion and applicants thereof
US6489901B1 (en) * 2001-08-31 2002-12-03 Cirrus Logic, Inc. Variable duty cycle resampling circuits and methods and sample rate converters using the same
US6608572B1 (en) * 2001-08-31 2003-08-19 Cirrus Logic, Inc. Analog to digital converters with integral sample rate conversion and systems and methods using the same
US6570514B1 (en) * 2001-12-21 2003-05-27 Scott R. Velazquez Linearity error compensator
US6542094B1 (en) * 2002-03-04 2003-04-01 Cirrus Logic, Inc. Sample rate converters with minimal conversion error and analog to digital and digital to analog converters using the same
US6642863B1 (en) * 2002-03-11 2003-11-04 Cirrus Logic, Inc. Sample rate converters using virtual sample rates and analog to digital and digital to analog converters using the same

Also Published As

Publication number Publication date
EP1569336B1 (de) 2010-04-07
US7126505B2 (en) 2006-10-24
US20050184889A1 (en) 2005-08-25
EP1569336A1 (de) 2005-08-31

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