DE19810003A1 - Verfahren zur Herstellung eines Halbleiterbauelementes mit dotierter Polysilizium-Zwischenverbindungsschicht - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelementes mit dotierter Polysilizium-Zwischenverbindungsschicht

Info

Publication number
DE19810003A1
DE19810003A1 DE19810003A DE19810003A DE19810003A1 DE 19810003 A1 DE19810003 A1 DE 19810003A1 DE 19810003 A DE19810003 A DE 19810003A DE 19810003 A DE19810003 A DE 19810003A DE 19810003 A1 DE19810003 A1 DE 19810003A1
Authority
DE
Germany
Prior art keywords
polysilicon layer
layer
doped polysilicon
further characterized
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19810003A
Other languages
German (de)
English (en)
Inventor
Dong-Yun Kim
Jae-Hak Baek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE19810003A1 publication Critical patent/DE19810003A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE19810003A 1997-11-03 1998-03-09 Verfahren zur Herstellung eines Halbleiterbauelementes mit dotierter Polysilizium-Zwischenverbindungsschicht Withdrawn DE19810003A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970057753A KR100252042B1 (ko) 1997-11-03 1997-11-03 도우프트 폴리실리콘막으로 구성된 배선을 갖는반도체소자의 제조방법

Publications (1)

Publication Number Publication Date
DE19810003A1 true DE19810003A1 (de) 1999-05-06

Family

ID=19524054

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19810003A Withdrawn DE19810003A1 (de) 1997-11-03 1998-03-09 Verfahren zur Herstellung eines Halbleiterbauelementes mit dotierter Polysilizium-Zwischenverbindungsschicht

Country Status (5)

Country Link
JP (1) JPH11145145A (ja)
KR (1) KR100252042B1 (ja)
CN (1) CN1216400A (ja)
DE (1) DE19810003A1 (ja)
TW (1) TW432627B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552273B (zh) * 2002-09-30 2011-10-26 张国飙 三维只读存储器
US7701058B2 (en) 2007-01-26 2010-04-20 International Business Machines Corporation Undoped polysilicon metal silicide wiring

Also Published As

Publication number Publication date
JPH11145145A (ja) 1999-05-28
KR100252042B1 (ko) 2000-05-01
KR19990038118A (ko) 1999-06-05
TW432627B (en) 2001-05-01
CN1216400A (zh) 1999-05-12

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: PATENTANWAELTE RUFF, WILHELM, BEIER, DAUSTER & PAR

8141 Disposal/no request for examination