DE19805500A1 - Vielzweck-Eingabe/Ausgabe-Schaltung für das Chiptesten - Google Patents
Vielzweck-Eingabe/Ausgabe-Schaltung für das ChiptestenInfo
- Publication number
- DE19805500A1 DE19805500A1 DE19805500A DE19805500A DE19805500A1 DE 19805500 A1 DE19805500 A1 DE 19805500A1 DE 19805500 A DE19805500 A DE 19805500A DE 19805500 A DE19805500 A DE 19805500A DE 19805500 A1 DE19805500 A1 DE 19805500A1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- signal
- event
- switching
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000012360 testing method Methods 0.000 title claims description 33
- 238000000034 method Methods 0.000 claims description 32
- 238000013461 design Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000013459 approach Methods 0.000 description 16
- PCHPORCSPXIHLZ-UHFFFAOYSA-N diphenhydramine hydrochloride Chemical group [Cl-].C=1C=CC=CC=1C(OCC[NH+](C)C)C1=CC=CC=C1 PCHPORCSPXIHLZ-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 241000486634 Bena Species 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000013213 extrapolation Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 244000309464 bull Species 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000035987 intoxication Effects 0.000 description 1
- 231100000566 intoxication Toxicity 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000742 single-metal deposition Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 239000012085 test solution Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/863,832 US6407613B1 (en) | 1997-05-27 | 1997-05-27 | Multipurpose test chip input/output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE19805500A1 true DE19805500A1 (de) | 1998-12-03 |
Family
ID=25341893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19805500A Withdrawn DE19805500A1 (de) | 1997-05-27 | 1998-02-11 | Vielzweck-Eingabe/Ausgabe-Schaltung für das Chiptesten |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6407613B1 (enExample) |
| JP (1) | JPH116867A (enExample) |
| DE (1) | DE19805500A1 (enExample) |
| GB (1) | GB2327273B (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040153850A1 (en) * | 2002-12-20 | 2004-08-05 | Schoenborn Zale T. | Apparatus and method for automated electrical validation to detect and analyze worst case SSO condition |
| US7352217B1 (en) * | 2003-06-26 | 2008-04-01 | Marvell Semiconductor Israel Ltd. | Lock phase circuit |
| US7609079B2 (en) * | 2006-03-02 | 2009-10-27 | Dialog Semiconductor Gmbh | Probeless DC testing of CMOS I/O circuits |
| TWI312076B (en) * | 2006-10-19 | 2009-07-11 | Via Tech Inc | Apparatus and related method for chip i/o test |
| TWI304889B (en) * | 2006-10-26 | 2009-01-01 | Via Tech Inc | Method and related apparatus for testing chip |
| US7945827B1 (en) * | 2006-12-28 | 2011-05-17 | Marvell International Technology Ltd. | Method and device for scan chain management of dies reused in a multi-chip package |
| KR100915822B1 (ko) * | 2007-12-11 | 2009-09-07 | 주식회사 하이닉스반도체 | 바운더리 스캔 테스트 회로 및 바운더리 스캔 테스트 방법 |
| CN101713813B (zh) * | 2008-10-06 | 2012-06-06 | 中兴通讯股份有限公司 | 片上系统芯片和对片上系统芯片进行测试的方法 |
| GB2484524A (en) * | 2010-10-14 | 2012-04-18 | Powervation Ltd | Pin programming a power supply controller |
| CN104090225B (zh) * | 2014-07-09 | 2017-02-15 | 四川和芯微电子股份有限公司 | 测试芯片管脚连通性的电路 |
| CN104090226B (zh) * | 2014-07-09 | 2017-01-18 | 四川和芯微电子股份有限公司 | 测试芯片管脚连通性的电路 |
| US11264906B2 (en) * | 2019-12-13 | 2022-03-01 | Analog Devices, Inc. | Compound pin driver controller |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4441075A (en) | 1981-07-02 | 1984-04-03 | International Business Machines Corporation | Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection |
| US5068603A (en) | 1987-10-07 | 1991-11-26 | Xilinx, Inc. | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
| JP3372052B2 (ja) * | 1991-06-06 | 2003-01-27 | テキサス インスツルメンツ インコーポレイテツド | 境界走査集積回路 |
| US5214682A (en) * | 1991-12-27 | 1993-05-25 | Vlsi Technology, Inc. | High resolution digitally controlled oscillator |
| US5534774A (en) * | 1992-04-23 | 1996-07-09 | Intel Corporation | Apparatus for a test access architecture for testing of modules within integrated circuits |
| US6029263A (en) * | 1994-06-30 | 2000-02-22 | Tandem Computers Incorporated | Interconnect testing using non-compatible scan architectures |
| US5592493A (en) * | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
| US5923621A (en) * | 1995-06-07 | 1999-07-13 | Cirrus Logic, Inc. | Clock doubler circuit with duty cycle control |
| US5729678A (en) * | 1996-03-04 | 1998-03-17 | Ag Communication Systems Corporation | Bus monitor system |
-
1997
- 1997-05-27 US US08/863,832 patent/US6407613B1/en not_active Expired - Lifetime
-
1998
- 1998-02-11 DE DE19805500A patent/DE19805500A1/de not_active Withdrawn
- 1998-05-07 GB GB9809763A patent/GB2327273B/en not_active Expired - Fee Related
- 1998-05-12 JP JP10146638A patent/JPH116867A/ja not_active Withdrawn
-
2001
- 2001-11-14 US US09/992,907 patent/US6535049B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20020030531A1 (en) | 2002-03-14 |
| JPH116867A (ja) | 1999-01-12 |
| GB9809763D0 (en) | 1998-07-08 |
| GB2327273A (en) | 1999-01-20 |
| US6407613B1 (en) | 2002-06-18 |
| US6535049B2 (en) | 2003-03-18 |
| GB2327273B (en) | 2002-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3709032C2 (enExample) | ||
| DE69224727T2 (de) | Schaltung mit eingebautem Selbsttest | |
| DE602004000228T2 (de) | Integrierte Halbleiterschaltungsanordnung mit Signalregenerator für Prüfsignale und dazugehörige automatische Entwurfs-Vorrichtung, -Verfahren und -Programme | |
| DE3130714C2 (enExample) | ||
| DE68925813T2 (de) | Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen | |
| DE19758841B4 (de) | Grenzabtastzellenkette | |
| DE69126848T2 (de) | Integrierte Halbleiterschaltung | |
| DE69314683T2 (de) | Verfahren und Gerät zum Prüfen von Ein-/Ausgabeverbindungen des Randsteckverbinders einer Schaltkreiskarte mit Boundary Scan | |
| DE4434927C2 (de) | Verfahren zum Testen einer Schaltungsplatine | |
| DE19805500A1 (de) | Vielzweck-Eingabe/Ausgabe-Schaltung für das Chiptesten | |
| DE602004009329T2 (de) | Verfahren und system zum selektiven maskieren von testantworten | |
| DE68923086T2 (de) | Verfahren zum Testen von hierarchisch organisierten integrierten Schaltungen und integrierte Schaltungen, geeignet für einen solchen Test. | |
| EP0010173A1 (de) | Halbleiterplättchen mit verbesserter Prüfbarkeit der monolithisch hochintegrierten Schaltungen | |
| DE60010614T2 (de) | On-line Prüfung des programmierbaren Verbindungsnetzwerks in einer feldprogrammierbaren Gatteranordnung | |
| DE3702408C2 (enExample) | ||
| DE69017169T2 (de) | Testen integrierter Schaltungen unter Verwendung von Taktgeberstössen. | |
| DE60110199T2 (de) | Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler | |
| DE3146721C2 (enExample) | ||
| DE3850547T2 (de) | Speicher mit eingebautem Logik-LSI und Verfahren zum LSI-Prüfen. | |
| DE4136061A1 (de) | Leiterplatten-pruefsystem | |
| DE60309761T2 (de) | Methode und Vorrichtung zum Testen von Hochgeschwindigkeits-Verbindungsschaltungen | |
| DE102013114895B4 (de) | Scan-Systeme und Verfahren | |
| DE69430304T2 (de) | Anordnung zum testen von verbindungen mit pulling-widerständen | |
| DE3918886A1 (de) | Ruecksetzanordnung in einer datenverarbeitungseinheit | |
| DE3486064T2 (de) | Logische schaltung mit eingebauter selbsttestfunktion. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| 8127 | New person/name/address of the applicant |
Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), |
|
| 8127 | New person/name/address of the applicant |
Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE |
|
| 8130 | Withdrawal |