JPH116867A - 多目的テスト・チップ入力／出力回路 - Google Patents

多目的テスト・チップ入力／出力回路

Info

Publication number
JPH116867A
JPH116867A JP10146638A JP14663898A JPH116867A JP H116867 A JPH116867 A JP H116867A JP 10146638 A JP10146638 A JP 10146638A JP 14663898 A JP14663898 A JP 14663898A JP H116867 A JPH116867 A JP H116867A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
event
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10146638A
Other languages
English (en)
Japanese (ja)
Other versions
JPH116867A5 (enExample
Inventor
Dwight Jaynes
ドゥワイト・ジェインズ
Michael D Bienek
マイケル・ディー・ビエネック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH116867A publication Critical patent/JPH116867A/ja
Publication of JPH116867A5 publication Critical patent/JPH116867A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP10146638A 1997-05-27 1998-05-12 多目的テスト・チップ入力／出力回路 Withdrawn JPH116867A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US863,832 1977-12-23
US08/863,832 US6407613B1 (en) 1997-05-27 1997-05-27 Multipurpose test chip input/output circuit

Publications (2)

Publication Number Publication Date
JPH116867A true JPH116867A (ja) 1999-01-12
JPH116867A5 JPH116867A5 (enExample) 2005-03-17

Family

ID=25341893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10146638A Withdrawn JPH116867A (ja) 1997-05-27 1998-05-12 多目的テスト・チップ入力／出力回路

Country Status (4)

Country Link
US (2) US6407613B1 (enExample)
JP (1) JPH116867A (enExample)
DE (1) DE19805500A1 (enExample)
GB (1) GB2327273B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040153850A1 (en) * 2002-12-20 2004-08-05 Schoenborn Zale T. Apparatus and method for automated electrical validation to detect and analyze worst case SSO condition
US7352217B1 (en) * 2003-06-26 2008-04-01 Marvell Semiconductor Israel Ltd. Lock phase circuit
US7609079B2 (en) * 2006-03-02 2009-10-27 Dialog Semiconductor Gmbh Probeless DC testing of CMOS I/O circuits
TWI312076B (en) * 2006-10-19 2009-07-11 Via Tech Inc Apparatus and related method for chip i/o test
TWI304889B (en) * 2006-10-26 2009-01-01 Via Tech Inc Method and related apparatus for testing chip
US7945827B1 (en) * 2006-12-28 2011-05-17 Marvell International Technology Ltd. Method and device for scan chain management of dies reused in a multi-chip package
KR100915822B1 (ko) * 2007-12-11 2009-09-07 주식회사 하이닉스반도체 바운더리 스캔 테스트 회로 및 바운더리 스캔 테스트 방법
CN101713813B (zh) * 2008-10-06 2012-06-06 中兴通讯股份有限公司 片上系统芯片和对片上系统芯片进行测试的方法
GB2484524A (en) * 2010-10-14 2012-04-18 Powervation Ltd Pin programming a power supply controller
CN104090225B (zh) * 2014-07-09 2017-02-15 四川和芯微电子股份有限公司 测试芯片管脚连通性的电路
CN104090226B (zh) * 2014-07-09 2017-01-18 四川和芯微电子股份有限公司 测试芯片管脚连通性的电路
US11264906B2 (en) * 2019-12-13 2022-03-01 Analog Devices, Inc. Compound pin driver controller

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441075A (en) 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US5068603A (en) 1987-10-07 1991-11-26 Xilinx, Inc. Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays
JP3372052B2 (ja) * 1991-06-06 2003-01-27 テキサス インスツルメンツ インコーポレイテツド 境界走査集積回路
US5214682A (en) * 1991-12-27 1993-05-25 Vlsi Technology, Inc. High resolution digitally controlled oscillator
US5534774A (en) * 1992-04-23 1996-07-09 Intel Corporation Apparatus for a test access architecture for testing of modules within integrated circuits
US6029263A (en) * 1994-06-30 2000-02-22 Tandem Computers Incorporated Interconnect testing using non-compatible scan architectures
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US5923621A (en) * 1995-06-07 1999-07-13 Cirrus Logic, Inc. Clock doubler circuit with duty cycle control
US5729678A (en) * 1996-03-04 1998-03-17 Ag Communication Systems Corporation Bus monitor system

Also Published As

Publication number Publication date
US20020030531A1 (en) 2002-03-14
US6535049B2 (en) 2003-03-18
DE19805500A1 (de) 1998-12-03
GB2327273B (en) 2002-02-13
GB9809763D0 (en) 1998-07-08
US6407613B1 (en) 2002-06-18
GB2327273A (en) 1999-01-20

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