DE19749600A1 - Takttreiberschaltung und integrierte Halbleiterschaltungseinrichtung - Google Patents

Takttreiberschaltung und integrierte Halbleiterschaltungseinrichtung

Info

Publication number
DE19749600A1
DE19749600A1 DE19749600A DE19749600A DE19749600A1 DE 19749600 A1 DE19749600 A1 DE 19749600A1 DE 19749600 A DE19749600 A DE 19749600A DE 19749600 A DE19749600 A DE 19749600A DE 19749600 A1 DE19749600 A1 DE 19749600A1
Authority
DE
Germany
Prior art keywords
clock
driver
clock driver
clock signal
gate array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19749600A
Other languages
English (en)
Other versions
DE19749600C2 (de
Inventor
Masaya Shirata
Tadayuki Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19749600A1 publication Critical patent/DE19749600A1/de
Application granted granted Critical
Publication of DE19749600C2 publication Critical patent/DE19749600C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
DE19749600A 1997-03-03 1997-11-10 Integrierte Halbleiterschaltungseinrichtung mit Makrozellenlayoutbereichen wie ein Gate-Array oder ein eingebettetes Zellen-Array (embedded cell array ECA), und im einzelnen eine in der integrierten Halbleiterschaltungseinrichtung vorgesehene Takttreiberschaltung Expired - Fee Related DE19749600C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9047912A JPH10246754A (ja) 1997-03-03 1997-03-03 クロックドライバ回路及び半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE19749600A1 true DE19749600A1 (de) 1998-09-10
DE19749600C2 DE19749600C2 (de) 2001-08-09

Family

ID=12788589

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19749600A Expired - Fee Related DE19749600C2 (de) 1997-03-03 1997-11-10 Integrierte Halbleiterschaltungseinrichtung mit Makrozellenlayoutbereichen wie ein Gate-Array oder ein eingebettetes Zellen-Array (embedded cell array ECA), und im einzelnen eine in der integrierten Halbleiterschaltungseinrichtung vorgesehene Takttreiberschaltung

Country Status (4)

Country Link
US (1) US5914625A (de)
JP (1) JPH10246754A (de)
KR (1) KR100258279B1 (de)
DE (1) DE19749600C2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000200114A (ja) 1999-01-07 2000-07-18 Nec Corp クロック分配回路
US6959132B2 (en) * 2002-03-13 2005-10-25 Pts Corporation One-to-M wavelength routing element
KR100429891B1 (ko) * 2002-07-29 2004-05-03 삼성전자주식회사 클럭 스큐를 최소화하기 위한 격자형 클럭 분배망
US20110270599A1 (en) * 2010-04-29 2011-11-03 Park Heat-Bit Method for testing integrated circuit and semiconductor memory device
US9305129B2 (en) * 2013-12-26 2016-04-05 Cavium, Inc. System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells
US9390209B2 (en) 2013-12-26 2016-07-12 Cavium, Inc. System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks
US9443053B2 (en) 2013-12-26 2016-09-13 Cavium, Inc. System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226943A (ja) * 1985-03-30 1986-10-08 Toshiba Corp 自動配置配線用標準セル
JPH0828421B2 (ja) * 1987-08-27 1996-03-21 株式会社東芝 半導体集積回路装置
JPH0384951A (ja) * 1989-08-29 1991-04-10 Mitsubishi Electric Corp 集積回路のレイアウト設計方法
US5254886A (en) * 1992-06-19 1993-10-19 Actel Corporation Clock distribution scheme for user-programmable logic array architecture
JP2826446B2 (ja) * 1992-12-18 1998-11-18 三菱電機株式会社 半導体集積回路装置及びその設計方法
JPH0714994A (ja) * 1993-06-17 1995-01-17 Fujitsu Ltd 半導体集積回路装置及び基準信号供給方法
JPH0722511A (ja) * 1993-07-05 1995-01-24 Mitsubishi Electric Corp 半導体装置
JPH07168735A (ja) * 1993-12-16 1995-07-04 Matsushita Electric Ind Co Ltd スキャンテスト方法およびクロックスキュー補正装置およびクロック配線方法

Also Published As

Publication number Publication date
KR19980079455A (ko) 1998-11-25
KR100258279B1 (ko) 2000-06-01
DE19749600C2 (de) 2001-08-09
JPH10246754A (ja) 1998-09-14
US5914625A (en) 1999-06-22

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee