DE1948923C3 - Verfahren zum Herstellen von Halbleiterbauelementen - Google Patents
Verfahren zum Herstellen von HalbleiterbauelementenInfo
- Publication number
- DE1948923C3 DE1948923C3 DE1948923A DE1948923A DE1948923C3 DE 1948923 C3 DE1948923 C3 DE 1948923C3 DE 1948923 A DE1948923 A DE 1948923A DE 1948923 A DE1948923 A DE 1948923A DE 1948923 C3 DE1948923 C3 DE 1948923C3
- Authority
- DE
- Germany
- Prior art keywords
- layer
- mask
- semiconductor substrate
- window
- etchant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US76557468A | 1968-10-07 | 1968-10-07 |
Publications (3)
Publication Number | Publication Date |
---|---|
DE1948923A1 DE1948923A1 (de) | 1970-04-16 |
DE1948923B2 DE1948923B2 (de) | 1977-04-14 |
DE1948923C3 true DE1948923C3 (de) | 1980-10-30 |
Family
ID=25073903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1948923A Expired DE1948923C3 (de) | 1968-10-07 | 1969-09-27 | Verfahren zum Herstellen von Halbleiterbauelementen |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS4829187B1 (enrdf_load_stackoverflow) |
DE (1) | DE1948923C3 (enrdf_load_stackoverflow) |
FR (1) | FR2020020B1 (enrdf_load_stackoverflow) |
GB (1) | GB1265199A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2020531C2 (de) * | 1970-04-27 | 1982-10-21 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur Herstellung von Silizium-Höchstfrequenz-Planartransistoren |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3479237A (en) * | 1966-04-08 | 1969-11-18 | Bell Telephone Labor Inc | Etch masks on semiconductor surfaces |
-
1969
- 1969-08-19 FR FR6928468A patent/FR2020020B1/fr not_active Expired
- 1969-09-22 GB GB1265199D patent/GB1265199A/en not_active Expired
- 1969-09-27 DE DE1948923A patent/DE1948923C3/de not_active Expired
- 1969-10-07 JP JP44079710A patent/JPS4829187B1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE1948923B2 (de) | 1977-04-14 |
FR2020020A1 (enrdf_load_stackoverflow) | 1970-07-10 |
DE1948923A1 (de) | 1970-04-16 |
GB1265199A (enrdf_load_stackoverflow) | 1972-03-01 |
FR2020020B1 (enrdf_load_stackoverflow) | 1974-09-20 |
JPS4829187B1 (enrdf_load_stackoverflow) | 1973-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0000327B1 (de) | Verfahren zum Herstellen von integrierten Halbleiteranordnungen durch Anwendung einer auf Selbstausrichtung basierenden Maskierungstechnik | |
DE1589810C3 (de) | Passiviertes Halbleiterbauelement und Verfahren zu seiner Herstellung | |
DE2729171C2 (de) | Verfahren zur Herstellung einer integrierten Schaltung | |
DE1764056B1 (de) | Verfahren zum herstellen einer halbleiteranordnung | |
DE3024084A1 (de) | Verfahren zur herstellung von halbleiterbauelementen | |
EP0012220A1 (de) | Verfahren zur Herstellung eines Schottky-Kontakts mit selbstjustierter Schutzringzone | |
DE2807138A1 (de) | Verfahren zum herstellen eines halbleiterbauelements | |
DE2633714C2 (de) | Integrierte Halbleiter-Schaltungsanordnung mit einem bipolaren Transistor und Verfahren zu ihrer Herstellung | |
DE2249832C3 (de) | Verfahren zum Herstellen einer Verdrahtungsschicht und Anwendung des Verfahrens zum Herstellen von Mehrschichtenverdrahtungen | |
DE2422120B2 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE2740757A1 (de) | Halbleiter mit mehrschichtiger metallisierung und verfahren zu dessen herstellung | |
DE2348199A1 (de) | Verfahren zur herstellung von mis-anordnungen | |
DE2923969C2 (de) | Verfahren zum Herstellen eines Feldeffekttransistors mit isoliertem Gate für integrierte Halbleiterschaltungen | |
DE2111633A1 (de) | Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors | |
DE1918054A1 (de) | Verfahren zur Herstellung von Halbleiter-Bauelementen | |
DE2451486C2 (de) | Verfahren zum Herstellen von integrierten Halbleiteranordnungen | |
DE2020531C2 (de) | Verfahren zur Herstellung von Silizium-Höchstfrequenz-Planartransistoren | |
DE1948923C3 (de) | Verfahren zum Herstellen von Halbleiterbauelementen | |
DE2453528C2 (de) | Maskierungsverfahren | |
DE69033515T2 (de) | Verfahren zur Herstellung einer integrierten Schaltung | |
DE2100292A1 (de) | Halbleiteranordnung mit relativ kleinen geometrischen Abmessungen und Verfahren zur Herstellung derselben | |
DE2139631C3 (de) | Verfahren zum Herstellen eines Halbleiterbauelements, bei dem der Rand einer Diffusionszone auf den Rand einer polykristallinen Siliciumelektrode ausgerichtet ist | |
DE3123348A1 (de) | Halbleiterbaustein und verfahren zu dessen herstellung | |
DE1564136C3 (de) | Verfahren zum Herstellen von Halbleiterbauelementen | |
DE1764937C3 (de) | Verfahren zur Herstellung von Isolationsschichten zwischen mehrschichtig übereinander angeordneten metallischen Leitungsverbindungen für eine Halbleiteranordnung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C3 | Grant after two publication steps (3rd publication) | ||
8339 | Ceased/non-payment of the annual fee |