DE1903870B2 - Verfahren zum herstellen monolithischer halbleiteranordnungen und nach dem verfahren hergestellte halbleiteranordnung - Google Patents

Verfahren zum herstellen monolithischer halbleiteranordnungen und nach dem verfahren hergestellte halbleiteranordnung

Info

Publication number
DE1903870B2
DE1903870B2 DE19691903870 DE1903870A DE1903870B2 DE 1903870 B2 DE1903870 B2 DE 1903870B2 DE 19691903870 DE19691903870 DE 19691903870 DE 1903870 A DE1903870 A DE 1903870A DE 1903870 B2 DE1903870 B2 DE 1903870B2
Authority
DE
Germany
Prior art keywords
zone
zones
epitaxial layer
pattern
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19691903870
Other languages
German (de)
English (en)
Other versions
DE1903870A1 (de
Inventor
Bernard Thomas New Providence N.J. Murphy (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE1903870A1 publication Critical patent/DE1903870A1/de
Publication of DE1903870B2 publication Critical patent/DE1903870B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/036—Diffusion, nonselective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/921—Nonselective diffusion

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE19691903870 1968-02-05 1969-01-27 Verfahren zum herstellen monolithischer halbleiteranordnungen und nach dem verfahren hergestellte halbleiteranordnung Withdrawn DE1903870B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70316468A 1968-02-05 1968-02-05

Publications (2)

Publication Number Publication Date
DE1903870A1 DE1903870A1 (de) 1969-10-30
DE1903870B2 true DE1903870B2 (de) 1977-03-24

Family

ID=24824290

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19691903870 Withdrawn DE1903870B2 (de) 1968-02-05 1969-01-27 Verfahren zum herstellen monolithischer halbleiteranordnungen und nach dem verfahren hergestellte halbleiteranordnung

Country Status (10)

Country Link
US (1) US3575741A (OSRAM)
BE (1) BE726241A (OSRAM)
CH (1) CH498493A (OSRAM)
DE (1) DE1903870B2 (OSRAM)
ES (1) ES363412A1 (OSRAM)
FR (1) FR1598853A (OSRAM)
GB (1) GB1259803A (OSRAM)
IE (1) IE32822B1 (OSRAM)
IL (1) IL31358A (OSRAM)
NL (1) NL6901818A (OSRAM)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3780426A (en) * 1969-10-15 1973-12-25 Y Ono Method of forming a semiconductor circuit element in an isolated epitaxial layer
US3716425A (en) * 1970-08-24 1973-02-13 Motorola Inc Method of making semiconductor devices through overlapping diffusions
JPS509635B1 (OSRAM) * 1970-09-07 1975-04-14
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3697827A (en) * 1971-02-09 1972-10-10 Unitrode Corp Structure and formation of semiconductors with transverse conductivity gradients
US3787253A (en) * 1971-12-17 1974-01-22 Ibm Emitter diffusion isolated semiconductor structure
GB1388926A (en) * 1972-03-04 1975-03-26 Ferranti Ltd Manufacture of silicon semiconductor devices
US4053336A (en) * 1972-05-30 1977-10-11 Ferranti Limited Method of manufacturing a semiconductor integrated circuit device having a conductive plane and a diffused network of conductive tracks
US3909807A (en) * 1974-09-03 1975-09-30 Bell Telephone Labor Inc Integrated circuit memory cell
US3971059A (en) * 1974-09-23 1976-07-20 National Semiconductor Corporation Complementary bipolar transistors having collector diffused isolation
US4067038A (en) * 1976-12-22 1978-01-03 Harris Corporation Substrate fed logic and method of fabrication
SU773793A1 (ru) * 1977-11-02 1980-10-23 Предприятие П/Я -6429 Способ изготовлени полупроводниковых интегральных бипол рных схем
JPS5632762A (en) * 1979-08-27 1981-04-02 Fujitsu Ltd Semiconductor device
GB8426897D0 (en) * 1984-10-24 1984-11-28 Ferranti Plc Fabricating semiconductor devices
US4969823A (en) * 1986-09-26 1990-11-13 Analog Devices, Incorporated Integrated circuit with complementary junction-isolated bipolar transistors and method of making same

Also Published As

Publication number Publication date
DE1903870A1 (de) 1969-10-30
NL6901818A (OSRAM) 1969-08-07
CH498493A (de) 1970-10-31
BE726241A (OSRAM) 1969-05-29
IE32822B1 (en) 1973-12-12
ES363412A1 (es) 1970-12-16
IE32822L (en) 1969-08-05
IL31358A0 (en) 1969-03-27
US3575741A (en) 1971-04-20
IL31358A (en) 1971-11-29
FR1598853A (OSRAM) 1970-07-06
GB1259803A (en) 1972-01-12

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