DE1564860A1 - Verfahren zur Herstellung von Halbleitervorrichtungen - Google Patents

Verfahren zur Herstellung von Halbleitervorrichtungen

Info

Publication number
DE1564860A1
DE1564860A1 DE19661564860 DE1564860A DE1564860A1 DE 1564860 A1 DE1564860 A1 DE 1564860A1 DE 19661564860 DE19661564860 DE 19661564860 DE 1564860 A DE1564860 A DE 1564860A DE 1564860 A1 DE1564860 A1 DE 1564860A1
Authority
DE
Germany
Prior art keywords
semiconductor
semiconductor body
switching elements
permanent
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19661564860
Other languages
German (de)
English (en)
Inventor
Cunningham James A Richardson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE1564860A1 publication Critical patent/DE1564860A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4821—Bridge structure with air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE19661564860 1965-06-30 1966-06-25 Verfahren zur Herstellung von Halbleitervorrichtungen Pending DE1564860A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US46819665A 1965-06-30 1965-06-30

Publications (1)

Publication Number Publication Date
DE1564860A1 true DE1564860A1 (de) 1969-10-16

Family

ID=23858806

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19661564860 Pending DE1564860A1 (de) 1965-06-30 1966-06-25 Verfahren zur Herstellung von Halbleitervorrichtungen

Country Status (3)

Country Link
JP (1) JPS503627B1 (enExample)
DE (1) DE1564860A1 (enExample)
GB (2) GB1153052A (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555273B2 (enExample) * 1973-11-09 1980-02-05
JPS5542573U (enExample) * 1978-09-14 1980-03-19
JPS5764877U (enExample) * 1980-10-06 1982-04-17
US4918505A (en) * 1988-07-19 1990-04-17 Tektronix, Inc. Method of treating an integrated circuit to provide a temperature sensor that is integral therewith
EP0996157B1 (en) * 1998-10-21 2005-08-03 STMicroelectronics S.r.l. Process for manufacturing integrated devices comprising microstructures and associated suspended electrical interconnections

Also Published As

Publication number Publication date
GB1153051A (en) 1969-05-21
GB1153052A (en) 1969-05-21
JPS503627B1 (enExample) 1975-02-07

Similar Documents

Publication Publication Date Title
DE2640525C2 (de) Verfahren zur Herstellung einer MIS-Halbleiterschaltungsanordnung
DE1514818C3 (enExample)
DE1614283C3 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE1439935A1 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE1903961A1 (de) Integrierte Halbleiteranordnung
DE2031333C3 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE2749607C3 (de) Halbleiteranordnung und Verfahren zu deren Herstellung
DE1944793A1 (de) Halbleiterbauelement
DE2546314A1 (de) Feldeffekt-transistorstruktur und verfahren zur herstellung
EP0101000A2 (de) Integrierte Bipolar- und Mos-Transistoren enthaltende Halbleiter-schaltung auf einem Chip und Verfahren zu ihrer Herstellung
DE1564191A1 (de) Verfahren zum elektrischen Isolieren verschiedener in einer integrierten oder monolithischen Halbleitervorrichtung zusammengefasster Schaltelemente gegeneinander und gegen das gemeinsame Substrat
EP0005185A1 (de) Verfahren zum gleichzeitigen Herstellen von Schottky-Sperrschichtdioden und ohmschen Kontakten nach dotierten Halbleiterzonen
EP0001574A1 (de) Halbleiteranordnung für Widerstandsstrukturen in hochintegrierten Schaltkreisen und Verfahren zur Herstellung dieser Halbleiteranordnung
DE2149766A1 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE3002740A1 (de) Verfahren zur ausbildung von substratelektroden bei mos-ics mit lokaler oxidation
DE2458410C2 (de) Herstellungsverfahren für eine Halbleiteranordnung
DE1564860A1 (de) Verfahren zur Herstellung von Halbleitervorrichtungen
DE3851991T2 (de) Bipolartransistoren.
DE10318422A1 (de) Hochfrequenz-Bipolartransistor und Verfahren zur Herstellung desselben
DE69215956T2 (de) Verfahren zum Herstellen eines Kontakts auf einem Halbleiterbauelement
DE1564136C3 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE2657822C2 (enExample)
DE2133977C3 (de) Halbleiterbauelement
DE2001468A1 (de) Verfahren zur Herstellung von Halbleiterbauelementen
DE2460653A1 (de) Verfahren zum aetzen von silicium