DE1564860A1 - Method of manufacturing semiconductor devices - Google Patents

Description

Process for manufacturing semiconductor devices

The invention relates to integrated circuits, and more particularly miniaturized electronic circuits, in which all necessary switching components on are combined on a common substrate, but are kept electrically isolated from one another.

The strong increase in interest in the micro-miniaturization and especially in the field of electronics, which generally regarded as ^one Microelectronics is called, is reflected in the semiconductors in the rapid development of integrated circuits. An integrated circuit is the formation of individual active and / or passive switching components for an electronic circuit on a single piece of semiconductor

Dr Ha / Ma

909842/0855

material,

material, preferably made of a single crystal, to be understood, with the individual components under formation connected to each other in terms of the desired support function are. Meanwhile, if a number of transistors and resistors are formed in a single substrate where the substrate forms the collector zone of each transistor, the transistors must for many switching purposes kept isolated from each other to avoid the collectors being interconnected; the transistors must also be isolated from the resistors be. Achieving adequate insulation between these components was one of the main tasks in the development of integrated circuits.

Many methods have been developed to solve this problem, but all of them have various disadvantages. One such process, referred to as P-N junction isolation, creates a series of islands made of a semiconductor material of a certain conductivity type formed in a substrate of a material of the opposite conductivity type and that The substrate is biased with respect to the rest of the circuit so that that separates the islands from the substrate The transition is never biased in the forward direction. The islands form the collector zones, of transistors and

909842/0 855 then

Subsequently, diffusions take place in these islands Formation of the base and emitter zones made. That However, the main problem with this method is that the self-capacitance of the isolation junctions creates an undesired coupling at high frequencies. The circuits and the bias values must also be designed in such a way that the insulating transitions are safe are never forward biased under normal operating conditions. Even if the Transitions that are biased in the reverse direction can be caused by leakage currents and the accumulation of charge carriers undesirable effects occur at the insulating transition.

Another method proposed for insulation consists of the insulating islands into which the components are placed can then be installed from the original panel material. Isolation is then carried out by selective diffusion of material of opposite conductivity type from each side of the wafer and completely through the plate so that the diffusion fronts intersect. One disadvantage with this Method consists in that the diffusions through the platelet require thin platelets and long diffusion times at high surface concentrations, which results in a high insulation capacity.

909842/0855 At

Another, U.S. Patent 3,158,788 method described is on the side of the semiconductor body next to the switching elements and interconnects a holder is attached and semiconductor material is removed to isolate the switching elements. At a Such an arrangement, however, the interconnections are usually not accessible to the connecting wires, since they are covered by the holder, and the leads must be relatively thick in order to be attached to the holder to run past.

With these difficulties in mind, the present invention is directed to providing an improved one Isolation method, whereby all the necessary switching components of an integrated circuit by a common Substrate are united and yet electrically isolated from one another. Another object of the invention is the creation of an integrated circuit in which the switching components through the substrate on which they are formed, are electrically isolated from each other? the isolating agents do not have a high inherent capacity, so that the respective integrated circuit is used at very high frequencies and switched very quickly can be. Another object is to provide a semiconductor device having a single crystal region or very small zones in or on a semiconductor substrate,

909842/0855

.ledooh

but isolated from it, formed in a simple manner can be; in particular, the invention relates to the manufacture of such a device in which conductive leads spread over the surface of the substrate in the form of a continuous film can be.

To carry out the invention, all the necessary switching components are first formed in a single-crystal semiconductor die which is mounted in a known manner on an insulating substrate; then leads and interconnections are created between the various switching components to form the desired switching function, whereupon channels or walls are etched between all the various interconnected switching components in order to remove the semiconductor material around and below the leads and interconnects down to the insulating substrate . As a result, all of the individual, interconnected components are isolated from one another by the etched walls or channels and by the insulating substrate. Although this method is particularly useful for making integrated circuits, it is also suitable for making individual transistors or the like that can be operated at very high frequencies. 9098 42/08 5 5

the

1564880

The invention is explained in more detail by the following description in conjunction with the drawing. In the drawing show:

fig. 1 to 4 are diagrammatic sectional views of a semiconductor die in the first stages of FIG inventive production of an integrated Circuit,

5 shows a diagrammatic representation of a small section from the Pig's plate. 1 to 4,

FIGS. 6 and 7 are sectional views of part of the detail of Fig. 5 along the line 6-6, from which later stages of the method according to the invention can be seen are,

8 shows a top view of the finished device 1 to 7 before the electrical insulation of the individual interconnected Switching components from each other,

FIG. 9 shows a diagrammatic representation of the finished device from FIG. 8 after the implementation of the invention Insulation,

909842/0855 *** ■ ¹⁰

Figure 10 is a sectional view of a portion of the finished Circuit of Fig. 9 along line 10-10,

FIG. 1t is a level diagram of that shown in FIG Cutout included integrated circuit, and

Fig. 12 is a diagrammatic sectional view showing the inventive production of a single Shows high frequency transistor.

1 explains the first stage of the method according to the invention. A platelet 10 made of a monocrystalline N + semiconductor material with a low specific resistance, for example silicon, the resistance of which is approximately 0.010 to 0.025 ohm.cm, is used as the starting material. This plate can have a diameter of about 25 mm and a thickness of about 0.25 mm. The top and bottom of the plate 10 are provided with insulating coatings 11 and 12, for example made of silicon oxide; these coatings are obtained in the usual way and have a thickness of perhaps 10,000 Å. The oxide coatings 11 and 12 can, for example, have grown thermally by exposing the platelet 10 to water vapor ^{at about 1200 ° C. for a long enough time.} Another method of forming the oxide layers 11 and 12 consists in the

909842/0855 »oxidative»

"oxidative" technique in which oxygen and tetraethoxysilane in the form of vapor at 250 to 500 ⁰ C in the presence of 10 Plättohens reacted together. The reaction mixture is obtained by bubbling oxygen through liquid tetraethoxysilane at room temperature, then combining the gas mixture with excess oxygen and passing it into a tube furnace containing the plate 10, where the oxidation takes place. The silicon oxide formed is deposited on the top and bottom of the plate 10. The advantage of this latter process lies in the relatively low temperatures at which uniform oxide coatings can be formed.

The next, in Pig. The stage of the invention shown in FIG. 2 consists in that the oxide-coated plate 10 comes into an epitaxial reactor, where the uppermost layer 13> is produced, which optionally later forms the substrate. In the reactor a layer 13 of semiconductor material is placed on top of the oxide coated chip 10 is deposited from the steam state. The most common method of vapor deposition is the hydrogen reduction of silicon tetrachloride, which is known to the person skilled in the art and no further details Needs explanation. The layer 13 can be K-conductive, P-conductive or be intrinsic and the actual crystal

909842/0855

tisrang

The orientation of the semiconductor layer 13 is not important, since their primary puncture is to form a support or basia on which the various Components of the integrated circuit are formed. Since the layer 13 is deposited on the oxide coating 11 however, it is most likely either polycrystalline or amorphous and not single crystalline. The thickness of the layer 13 should be about 0.175 to 0.2 mm to facilitate handling without breaking. The structure of Figure 2 then undergoes a lapping and polishing treatment subjected to the Oxydschioht 12 and almost the entire N + conductive semiconductor material 10 with little Resistance to remove except for a thin portion about 0.025mm thick. The lapped and polished The structure is then rotated by 180 °} This structure is shown in FIG. 3, the layer 13 now being the The substrate forms and the semiconductor material 10 with a low specific resistance of this substrate duroh the Oxydsohioht 11 is separated.

As the next process step, the structure of Fig. Is subjected to an epitaxial precipitation, wherein, as shown in FIG. 4, a layer 14 of N-conductive High resistivity semiconductor material on the low resistivity substrate 10 being knocked down. The Sohioht 14 with high resistance

909842/0855

serves

now serves as a zone in which to manufacture different components of an integrated circuit then diffusions are made or on from which epitaxial crackdowns are made can.

In this connection, reference is made to Fig. 5, where a small excerpt from the in Pig. 4 shown Plate is marked with 20? this cutout or this plate 20 is from an integrated circuit occupied. Bas original platelets would in undivided form dozens or even hundreds of cutouts, such as the cutout 20 included. An oxide layer 15, e.g. 20 so that it completely covers the high resistance layer 14 · Using photographic masking and etching techniques similar to Are known to those skilled in the art, certain parts of the oxide layer 15 are removed in the form of the patterns 30 to 34 (see Fig.5), so that corresponding parts of the high resistance layer 14 are exposed below the oxide layer 15. A cross-sectional view through part of the lamina 20 is shown in FIG. It should be noted that the exposed Parts of the substrate 14 with high resistance form the regions into which now subsequent diffusions to generate the various components of an integrated Sftha ^ ftinfc.

Jig. 7th

7 shows a sectional view of part of a finished integrated circuit with an NPN transistor T-. and a resistor H ^ formed by diffusion in the N-type layer. A P-conducting, diffused zone forms the base of the transistor, while an elongated P-conducting zone, formed at the same time as the base, forms _{the resistor R 1.} An N-conducting, diffused zone forms the emitter zone of the transistor T ... A silicon oxide masking is used for the diffusion, so that the oxide layer 15 has a stepped shape in the finished device. Apertures are made in the oxide where a connection is required and a metal film is then deposited over the oxide and selectively removed to form the desired connections and interconnections. The interconnection 21 thus connects the base of the transistor T .. with one end of the resistor R- and the metallic areas 25 and 26 form the emitter or. Collector connection. To achieve a contact with low resistance with the collector zone of the transistor Τ., It may be useful to first create an N + zone with low resistance by diffusion at the point

to form where the lead 26 makes an ohmic contact t

should result *

the 9 0 984 2/08 5 5

The formation of leads or interconnections, for example 21, 25 and 26, can be carried out in a conventionally known manner, for example by vacuum evaporation, and the leads themselves can consist of any suitable material. According to a preferred embodiment, however, a material is used for the leads or interconnections which, by its presence, does not degrade the semiconductor device, blends in well with the other treatments to which the device is subjected and allows working with very small geometrical dimensions. In the specific case of silicon semiconductor devices, contacts and interconnects must be found which adhere well to silicon and the silicon oxide surfaces without, however, reacting unfavorably with them, which can be used in conjunction with the common photo masking materials and etching methods which ^{see an ohm 1} electrical connection with little Resistance results with silicon, which can easily be applied by metal vapor deposition, which have high conductivity and can be connected with gold wires. A combination of metals, which fulfills all of the above tasks in an almost unique way, is molybdenum and gold. Accordingly, a thin molybdenum film is first applied to the entire surface of the silicon wafer 20 with the silicon oxide coating 15 and the etched contact points.

909842/0855

brings.

• brought. Then the molybdenum is covered with a thin gold film and then the gold and the Molybdenum etched away at the unwanted places, so that the desired connection and connection pattern 21, 25 and 26 remains on the silicon surface and on the oxide.

8 shows a plan view of the plate 20 Formation of the individual switching components and after suppression of the feeds and interconnections at the desired locations. At this stage of the procedure are the individual switching components in the plate 20 formed, Jedooh not yet electrically isolated from each other.

The electrical insulation of each of the switching components from the other is done by forming a series of channels or ridges which each component completely surrounded as this fig. 9 shows. The various feedings between the components then cross the channels to form the desired interconnections.

The formation of ramparts or canals takes place after the below in relation to Pig. 10 described photographisohen Masking and Xtz Method V Pig. 10 represents a partial sonittansioht by the plate 20 by the

909842/0855

channels

Channels 35 and 36. A layer of a photo etch protective material of the type described in U.S. Patents 2,670,285, 2,670,286, and 2,670,287, or the type available from the Eastman Kodak Company under the trade designation "KMBR" or " KTFR "is applied to the top of the wafer 20, with ¹¹ KTFR" being preferred. A photo masking ring is then applied to the photosensitive anti-etch layer which covers the areas where the channels or walls are to be formed; -masked parts of the photo-etch protection layer are then exposed and photographically developed. The upper side of the plate 20 is then treated with etching agents which selectively remove the oxide layer 15 and the silicon layers 14 and 10 underneath in the masked areas down to the oxide layer 11, the feeds and interconnections remaining intact and the channels 35 and 36 shown, for example, in FIG. 10 being formed.

The etchant used in each case should not attack the feeds and intermediate connections. For example, an integrated circuit in the manner described with leads made of molybdenum and gold or interconnections made. JTaehd © «the plate with the soalt components formed therein with the

909 8 42/0855 Photo etching certificate

Photo-etch protection layer and the masking on the described Art had been coated, the top of the wafer 20 was coated with an acid ammonium bifluoride (NR-HFp) treats existing chemical etchants, which selectively parts of the silicon oxide layer 15 below removed from inlets 21 and 26 (the extent of removal is shown by dashed line 15A), However, the silicon underneath was essentially not attacked. The masked surface the plaque was then washed with one of a mixture of nitric acid, hydrofluoric acid, and acetic acid Existing chemical etchant treated, which selectively parts of the silicon layers 14 and 10 below of the dashed lines 15A removed, while the remaining part of the silicon oxide layer 15 and the Silicon oxide layer 11 was not attacked.

The structure obtained is shown in FIG. 10, where eB the components T ₁ and R ₁ are electrically isolated from one another by the wall or channel 36 and the oxide layer and the feed or interconnection 21 bridges the gap between these switching components. When the usual metal deposition methods are used, the interconnection 21 is not attacked by the etching and remains very strong, although it bridges the channel 36. The bridges-

909842/085: 5 * · educational

- IO - ·

Forming feeds also withstood further processing, for example spraying the structure with alcohol under high pressure to remove the photo-etch protection material used without breaking the self-supporting or bridging parts. If necessary, the strength of the self-supporting leads can be increased by electrolytically plating gold by means of a suitable masking, for example made of KMER, which increases the strength. 9 shows the finished device obtained as a product of the method described above, the transistors T. and Tg and the resistors R ₁ , R ₃ and Rt being completely isolated from one another by the plate 20 and the interconnections consisting of a metal film forming a logic circuit as shown in FIG. 11.

Although the invention has been described above with reference to a specific method and embodiment it is of course not limited to this * The basic principle of the invention consists in the isolation of individual, connecting components connected by interconnections through the substrate in which these components are sandwiched by etching away certain parts of the material they were formed with chemical caustics,

909842/0855 which

ORIGINAL INSPECTED

which do not attack the interconnections Every method or every etching agent that fulfills this task falls within the scope except those described the invention.

Except for the described production of certain integrated Circuit can use the method according to the invention of course also for the production of a multitude of sound switching elements find application in a single substrate. For example, in addition to transistors, diodes and resistors, other components such as metal csyclli & J.li-conductor devices, Field effect transistors and dielectric Oxide capacitors are generated, which are connected to each other while performing the desired switching functions and then according to the invention vcaeinanäer electrically to be isolated. Although that is the starting material serving platelets in the described *! AusiuJirungsfcrm made of N + semiconductor material with low specific * If there was resistance, P-Isitend's materials can also do and / or those with high resistivity are used will.

Although the above-described method 'particularly for integrated circuits has proven to be suitable, but it is suitable also for the preparation of einzsl- Lien _t on an insulating substrate arranged Vorrich-

909842/0 855

dip.

services. With regard to this latter embodiment of the invention, reference is made to FIG. 12, which shows an SPH transistor 4-0, which consists of an N-conducting collector tube 44, a P-conducting, diffused base zone 45 and an N-conducting, diffused smitterasone 46 'consists. The transistor 40 is formed on the semiconductor substrate 41, from which it is separated by the oxide layer 42 in much the same way as described above with reference to the transistor 9? - by Pig. 1 to 11 was written. This process leaves an oxide coating 57 on the top of the wafer ©, which is all-stepped because of the successive diffusion treatments. For high frequency applications, the geometric dimensions of the active part of transistor 40 are extremely small; the emitter region is 46 in some cases

only a few hundredths of a mil.

The collector, base and transmitter soles of this transistor are formed by metal strips 51 or 56 or 48, which are etched into openings in the oxide coating 57 ragan and see an ohm with the corresponding zones Contact. The strips end in widened overlays 52, 55 and 49

This broadened contact arrangement is for high frequency devices because of the extreme 909842/0855 mentioned above

Smallness

ORIGINAL INSPECTED

Smallness of the active zones of the transistor 40 is necessary. If the contacts are not wider than the active zones, it is impossible to make these contacts with to connect the outer lead wires, which is why the widened thin strips (which are connected to the active Zones have contact) with the widened supports (which result in the outer connections) are. With this widened contact arrangement, however, a capacitive reactance is connected because the widened contacts extend over oxide film 57 (which acts as a dielectric layer); this capacitive reactance causes undesirable coupling at high frequencies.

In order to reduce these capacitive effects, the channel or wall 47 becomes completely active around it Portions of transistor 40 are etched as shown in FIG. 12, removing these active areas from the widened supports and isolated from substantial portions of the elongated metal strips. The channel 47 is formed in the same manner as described above with reference to Figs. As a result, you get one High-frequency transistor 40 with small geometrical dimensions, in which thin, film-shaped, continuous metallic leads run from various active zones to the respective connection points while

909842/0 85 5

simultaneously

at the same time the one that is available with such an arrangement capacitive reactance kept to a minimum will. In order to further reduce any coupling capacity, channels or walls can also be formed in the same way, which completely cover each of the di © connection or Surrounding pads forming connection points and isolating them from one another.

The invention can be modified widely without departing from its scope.

Claims

909842/0855

mSPECTED

Claims (7)

Pat entana claims 1) Method of manufacturing a semiconductor device with several P- and N-conductive zones a surface of a semiconductor body with at least one PN junction ending at this surface in between, an insulator on this surface with at least one opening therein through which the by the PN junction enclosed zone is exposed, characterized in that on the opposite Side of the semiconductor body a permanent holder is attached that the first surface selectively masked and semiconductor material is removed from the semiconductor body. 2) The method of claim 1, wherein the semiconductor device is a semiconductor circuit having a plurality of switching elements is close to the one surface of the semiconductor body, which is through the conductive material are electrically connected to one another on the insulator, characterized in that semiconductor material is made of the semiconductor body between certain switching elements is removed in order to make these switching elements electrical isolate from each other. Il 909842/0855
'ORIGINAL! WSPECTEO 3) Method naoh claim 2, characterized gekennzeiohnet, that the semiconductor body is first attached to the permanent! rager, whereupon the switching elements generated and electrically connected to each other. 4) Method according to one of the preceding claims, characterized in that the permanent carrier consists of an oxide layer adjoining the semiconductor body consists. 5) Method according to claim 4, characterized in that the permanent support is adjacent to the oxide layer contains a deposited semiconductor layer. 6) Method according to one of the preceding claims, characterized in that semiconductor material by means of the insulator, the conductive material and etchant non-corrosive to the permanent support is removed. 7) Method according to one of the preceding claims, characterized in that the below the conductive Material located part of the semiconductor body 909842/0855 ORIGUNAL INSPECTED body is removed »while another part of the semiconductor body on which the conductive Material ends, remains * 909842/0855 "_ BNAt INSPECTED. - I. Blank page