DE1524163B1 - Binärer Akkumulator - Google Patents

Binärer Akkumulator

Info

Publication number
DE1524163B1
DE1524163B1 DE1966I0031287 DEI0031287A DE1524163B1 DE 1524163 B1 DE1524163 B1 DE 1524163B1 DE 1966I0031287 DE1966I0031287 DE 1966I0031287 DE I0031287 A DEI0031287 A DE I0031287A DE 1524163 B1 DE1524163 B1 DE 1524163B1
Authority
DE
Germany
Prior art keywords
input
flip
flop
output
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE1966I0031287
Other languages
German (de)
English (en)
Inventor
John Goodell Earle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE1524163B1 publication Critical patent/DE1524163B1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE1966I0031287 1965-07-12 1966-07-09 Binärer Akkumulator Withdrawn DE1524163B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US471021A US3340388A (en) 1965-07-12 1965-07-12 Latched carry save adder circuit for multipliers

Publications (1)

Publication Number Publication Date
DE1524163B1 true DE1524163B1 (de) 1970-03-05

Family

ID=23869960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1966I0031287 Withdrawn DE1524163B1 (de) 1965-07-12 1966-07-09 Binärer Akkumulator

Country Status (6)

Country Link
US (1) US3340388A (cg-RX-API-DMAC7.html)
DE (1) DE1524163B1 (cg-RX-API-DMAC7.html)
FR (1) FR1485087A (cg-RX-API-DMAC7.html)
GB (1) GB1104570A (cg-RX-API-DMAC7.html)
NL (1) NL152997B (cg-RX-API-DMAC7.html)
SE (1) SE324474B (cg-RX-API-DMAC7.html)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1549477B1 (de) * 1966-08-31 1971-03-25 Ibm Einrichtung zur schnellen akkumulation einer anzahl mehr stelliger binaerer operanden
DE2814078A1 (de) * 1977-04-28 1978-11-09 Ibm Addierschaltung mit zeitweiliger zwischenspeicherung des uebertrags
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
EP0298658A3 (en) * 1987-07-08 1990-07-11 AT&T Corp. Computational apparatus
EP0477011A3 (en) * 1990-09-20 1993-05-19 Oki Electric Industry Co., Ltd. Processor element, processing unit, and processor

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508038A (en) * 1966-08-30 1970-04-21 Ibm Multiplying apparatus for performing division using successive approximate reciprocals of a divisor
US5818743A (en) 1995-04-21 1998-10-06 Texas Instruments Incorporated Low power multiplier
US7392277B2 (en) * 2001-06-29 2008-06-24 Intel Corporation Cascaded domino four-to-two reducer circuit and method
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US7284029B2 (en) * 2003-11-06 2007-10-16 International Business Machines Corporation 4-to-2 carry save adder using limited switching dynamic logic

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964652A (en) * 1956-11-15 1960-12-13 Ibm Transistor switching circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1320034A (fr) * 1960-12-19 1963-03-08 Ibm Dispositifs de calcul numérique utilisant un seul type de circuit logique
US3207922A (en) * 1961-10-02 1965-09-21 Ibm Three-level inverter and latch circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964652A (en) * 1956-11-15 1960-12-13 Ibm Transistor switching circuits

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1549477B1 (de) * 1966-08-31 1971-03-25 Ibm Einrichtung zur schnellen akkumulation einer anzahl mehr stelliger binaerer operanden
DE2814078A1 (de) * 1977-04-28 1978-11-09 Ibm Addierschaltung mit zeitweiliger zwischenspeicherung des uebertrags
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
EP0298658A3 (en) * 1987-07-08 1990-07-11 AT&T Corp. Computational apparatus
EP0477011A3 (en) * 1990-09-20 1993-05-19 Oki Electric Industry Co., Ltd. Processor element, processing unit, and processor

Also Published As

Publication number Publication date
NL152997B (nl) 1977-04-15
US3340388A (en) 1967-09-05
SE324474B (cg-RX-API-DMAC7.html) 1970-06-01
NL6609727A (cg-RX-API-DMAC7.html) 1967-01-13
GB1104570A (en) 1968-02-28
FR1485087A (fr) 1967-06-16

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Legal Events

Date Code Title Description
E77 Valid patent as to the heymanns-index 1977
EHJ Ceased/non-payment of the annual fee