NL6609727A - - Google Patents
Info
- Publication number
- NL6609727A NL6609727A NL6609727A NL6609727A NL6609727A NL 6609727 A NL6609727 A NL 6609727A NL 6609727 A NL6609727 A NL 6609727A NL 6609727 A NL6609727 A NL 6609727A NL 6609727 A NL6609727 A NL 6609727A
- Authority
- NL
- Netherlands
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
- G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US471021A US3340388A (en) | 1965-07-12 | 1965-07-12 | Latched carry save adder circuit for multipliers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| NL6609727A true NL6609727A (cg-RX-API-DMAC7.html) | 1967-01-13 |
| NL152997B NL152997B (nl) | 1977-04-15 |
Family
ID=23869960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL666609727A NL152997B (nl) | 1965-07-12 | 1966-07-11 | Volledige binaire optelketen. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3340388A (cg-RX-API-DMAC7.html) |
| DE (1) | DE1524163B1 (cg-RX-API-DMAC7.html) |
| FR (1) | FR1485087A (cg-RX-API-DMAC7.html) |
| GB (1) | GB1104570A (cg-RX-API-DMAC7.html) |
| NL (1) | NL152997B (cg-RX-API-DMAC7.html) |
| SE (1) | SE324474B (cg-RX-API-DMAC7.html) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3508038A (en) * | 1966-08-30 | 1970-04-21 | Ibm | Multiplying apparatus for performing division using successive approximate reciprocals of a divisor |
| US3515344A (en) * | 1966-08-31 | 1970-06-02 | Ibm | Apparatus for accumulating the sum of a plurality of operands |
| US4110832A (en) * | 1977-04-28 | 1978-08-29 | International Business Machines Corporation | Carry save adder |
| DE3524981A1 (de) * | 1985-07-12 | 1987-01-22 | Siemens Ag | Anordnung mit einem saettigbaren carry-save-addierer |
| US4943909A (en) * | 1987-07-08 | 1990-07-24 | At&T Bell Laboratories | Computational origami |
| JP3228927B2 (ja) * | 1990-09-20 | 2001-11-12 | 沖電気工業株式会社 | プロセッサエレメント、プロセッシングユニット、プロセッサ、及びその演算処理方法 |
| US5818743A (en) | 1995-04-21 | 1998-10-06 | Texas Instruments Incorporated | Low power multiplier |
| US7392277B2 (en) * | 2001-06-29 | 2008-06-24 | Intel Corporation | Cascaded domino four-to-two reducer circuit and method |
| GB2396708B (en) * | 2002-12-05 | 2006-06-21 | Micron Technology Inc | Hybrid arithmetic logic unit |
| US7284029B2 (en) * | 2003-11-06 | 2007-10-16 | International Business Machines Corporation | 4-to-2 carry save adder using limited switching dynamic logic |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2964652A (en) * | 1956-11-15 | 1960-12-13 | Ibm | Transistor switching circuits |
| FR1320034A (fr) * | 1960-12-19 | 1963-03-08 | Ibm | Dispositifs de calcul numérique utilisant un seul type de circuit logique |
| US3207922A (en) * | 1961-10-02 | 1965-09-21 | Ibm | Three-level inverter and latch circuits |
-
1965
- 1965-07-12 US US471021A patent/US3340388A/en not_active Expired - Lifetime
-
1966
- 1966-06-22 FR FR7922A patent/FR1485087A/fr not_active Expired
- 1966-07-07 SE SE9309/66A patent/SE324474B/xx unknown
- 1966-07-09 DE DE1966I0031287 patent/DE1524163B1/de not_active Withdrawn
- 1966-07-11 GB GB31015/66A patent/GB1104570A/en not_active Expired
- 1966-07-11 NL NL666609727A patent/NL152997B/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NL152997B (nl) | 1977-04-15 |
| US3340388A (en) | 1967-09-05 |
| SE324474B (cg-RX-API-DMAC7.html) | 1970-06-01 |
| DE1524163B1 (de) | 1970-03-05 |
| GB1104570A (en) | 1968-02-28 |
| FR1485087A (fr) | 1967-06-16 |