FR1485087A - Circuit additionneur à maintien de retenue et à verrouillage multiplicateurs et ensembles additionneurs en comportant application - Google Patents

Circuit additionneur à maintien de retenue et à verrouillage multiplicateurs et ensembles additionneurs en comportant application

Info

Publication number
FR1485087A
FR1485087A FR7922A FR06007922A FR1485087A FR 1485087 A FR1485087 A FR 1485087A FR 7922 A FR7922 A FR 7922A FR 06007922 A FR06007922 A FR 06007922A FR 1485087 A FR1485087 A FR 1485087A
Authority
FR
France
Prior art keywords
adder
latching
carry
holding
including application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7922A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR1485087A publication Critical patent/FR1485087A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7922A 1965-07-12 1966-06-22 Circuit additionneur à maintien de retenue et à verrouillage multiplicateurs et ensembles additionneurs en comportant application Expired FR1485087A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US471021A US3340388A (en) 1965-07-12 1965-07-12 Latched carry save adder circuit for multipliers

Publications (1)

Publication Number Publication Date
FR1485087A true FR1485087A (fr) 1967-06-16

Family

ID=23869960

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7922A Expired FR1485087A (fr) 1965-07-12 1966-06-22 Circuit additionneur à maintien de retenue et à verrouillage multiplicateurs et ensembles additionneurs en comportant application

Country Status (6)

Country Link
US (1) US3340388A (fr)
DE (1) DE1524163B1 (fr)
FR (1) FR1485087A (fr)
GB (1) GB1104570A (fr)
NL (1) NL152997B (fr)
SE (1) SE324474B (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508038A (en) * 1966-08-30 1970-04-21 Ibm Multiplying apparatus for performing division using successive approximate reciprocals of a divisor
US3515344A (en) * 1966-08-31 1970-06-02 Ibm Apparatus for accumulating the sum of a plurality of operands
US4110832A (en) * 1977-04-28 1978-08-29 International Business Machines Corporation Carry save adder
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
US4943909A (en) * 1987-07-08 1990-07-24 At&T Bell Laboratories Computational origami
JP3228927B2 (ja) * 1990-09-20 2001-11-12 沖電気工業株式会社 プロセッサエレメント、プロセッシングユニット、プロセッサ、及びその演算処理方法
US5818743A (en) 1995-04-21 1998-10-06 Texas Instruments Incorporated Low power multiplier
US7392277B2 (en) * 2001-06-29 2008-06-24 Intel Corporation Cascaded domino four-to-two reducer circuit and method
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US7284029B2 (en) * 2003-11-06 2007-10-16 International Business Machines Corporation 4-to-2 carry save adder using limited switching dynamic logic

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964652A (en) * 1956-11-15 1960-12-13 Ibm Transistor switching circuits
US3094614A (en) * 1960-12-19 1963-06-18 Ibm Full adder and subtractor using nor logic
US3207922A (en) * 1961-10-02 1965-09-21 Ibm Three-level inverter and latch circuits

Also Published As

Publication number Publication date
NL6609727A (fr) 1967-01-13
SE324474B (fr) 1970-06-01
DE1524163B1 (de) 1970-03-05
US3340388A (en) 1967-09-05
NL152997B (nl) 1977-04-15
GB1104570A (en) 1968-02-28

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