DE112022007753B4 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung

Info

Publication number
DE112022007753B4
DE112022007753B4 DE112022007753.0T DE112022007753T DE112022007753B4 DE 112022007753 B4 DE112022007753 B4 DE 112022007753B4 DE 112022007753 T DE112022007753 T DE 112022007753T DE 112022007753 B4 DE112022007753 B4 DE 112022007753B4
Authority
DE
Germany
Prior art keywords
conductor layer
semiconductor device
insulating substrate
overhang
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE112022007753.0T
Other languages
German (de)
English (en)
Other versions
DE112022007753T5 (de
Inventor
Yuji Imoto
Naohiro Ogushi
Seiichiro Inokuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE112022007753T5 publication Critical patent/DE112022007753T5/de
Application granted granted Critical
Publication of DE112022007753B4 publication Critical patent/DE112022007753B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
DE112022007753.0T 2022-09-09 2022-09-09 Halbleitervorrichtung Active DE112022007753B4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/033850 WO2024053084A1 (ja) 2022-09-09 2022-09-09 半導体装置

Publications (2)

Publication Number Publication Date
DE112022007753T5 DE112022007753T5 (de) 2025-06-18
DE112022007753B4 true DE112022007753B4 (de) 2026-01-22

Family

ID=90192474

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022007753.0T Active DE112022007753B4 (de) 2022-09-09 2022-09-09 Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US20250329659A1 (https=)
JP (1) JP7802187B2 (https=)
CN (1) CN119768912A (https=)
DE (1) DE112022007753B4 (https=)
WO (1) WO2024053084A1 (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039539B1 (en) * 1999-03-26 2012-07-11 Kabushiki Kaisha Toshiba Method for producing a ceramic circuit board
DE102019135373A1 (de) * 2018-12-21 2020-06-25 Denso Corporation Halbleitervorrichtung und Verfahren zum Herstellen derselben

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064168A (ja) * 2000-08-17 2002-02-28 Toshiba Eng Co Ltd 冷却装置、冷却装置の製造方法および半導体装置
JP5338543B2 (ja) 2009-07-27 2013-11-13 日亜化学工業株式会社 光半導体装置及びその製造方法
JP5860599B2 (ja) 2011-03-01 2016-02-16 昭和電工株式会社 絶縁回路基板、パワーモジュール用ベースおよびその製造方法
JP6201490B2 (ja) 2013-07-30 2017-09-27 株式会社豊田自動織機 半導体装置
JP6304974B2 (ja) 2013-08-27 2018-04-04 三菱電機株式会社 半導体装置
JP6210818B2 (ja) 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
JP6607105B2 (ja) 2016-03-22 2019-11-20 三菱マテリアル株式会社 回路基板及び半導体モジュール、回路基板の製造方法
JP6867671B2 (ja) 2016-10-20 2021-05-12 トレックス・セミコンダクター株式会社 半導体装置の製造方法および半導体装置
JP6815217B2 (ja) 2017-02-09 2021-01-20 エイブリック株式会社 半導体装置
JP7450769B2 (ja) 2020-12-29 2024-03-15 三菱電機株式会社 半導体装置の製造方法、半導体装置用基板の製造方法、半導体装置及び電力変換装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039539B1 (en) * 1999-03-26 2012-07-11 Kabushiki Kaisha Toshiba Method for producing a ceramic circuit board
DE102019135373A1 (de) * 2018-12-21 2020-06-25 Denso Corporation Halbleitervorrichtung und Verfahren zum Herstellen derselben

Also Published As

Publication number Publication date
US20250329659A1 (en) 2025-10-23
JPWO2024053084A1 (https=) 2024-03-14
JP7802187B2 (ja) 2026-01-19
WO2024053084A1 (ja) 2024-03-14
DE112022007753T5 (de) 2025-06-18
CN119768912A (zh) 2025-04-04

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Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0023498000

Ipc: H10W0070620000