DE112010002747B4 - Verfahren zur Herstellung eines Siliziumepitaxialwafers - Google Patents

Verfahren zur Herstellung eines Siliziumepitaxialwafers Download PDF

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Publication number
DE112010002747B4
DE112010002747B4 DE112010002747.1T DE112010002747T DE112010002747B4 DE 112010002747 B4 DE112010002747 B4 DE 112010002747B4 DE 112010002747 T DE112010002747 T DE 112010002747T DE 112010002747 B4 DE112010002747 B4 DE 112010002747B4
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DE
Germany
Prior art keywords
silicon
crystal substrate
wafer
silicon crystal
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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DE112010002747.1T
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German (de)
English (en)
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DE112010002747T5 (de
Inventor
Tadashi Kawashima
Masahiro Yoshikawa
Akira Inoue
Yoshiya Yoshida
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Sumco Corp
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Sumco Corp
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Publication of DE112010002747T5 publication Critical patent/DE112010002747T5/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies

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  • Recrystallisation Techniques (AREA)
  • Chemical Vapour Deposition (AREA)
DE112010002747.1T 2009-06-29 2010-05-28 Verfahren zur Herstellung eines Siliziumepitaxialwafers Active DE112010002747B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009-153496 2009-06-29
JP2009153496A JP5609025B2 (ja) 2009-06-29 2009-06-29 エピタキシャルシリコンウェーハの製造方法
PCT/JP2010/059089 WO2011001770A1 (ja) 2009-06-29 2010-05-28 エピタキシャルシリコンウェーハとその製造方法

Publications (2)

Publication Number Publication Date
DE112010002747T5 DE112010002747T5 (de) 2013-09-26
DE112010002747B4 true DE112010002747B4 (de) 2020-12-24

Family

ID=43410851

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112010002747.1T Active DE112010002747B4 (de) 2009-06-29 2010-05-28 Verfahren zur Herstellung eines Siliziumepitaxialwafers

Country Status (4)

Country Link
US (1) US8659020B2 (https=)
JP (1) JP5609025B2 (https=)
DE (1) DE112010002747B4 (https=)
WO (1) WO2011001770A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5338559B2 (ja) * 2009-08-19 2013-11-13 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP6009237B2 (ja) * 2012-06-18 2016-10-19 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ
JP5845143B2 (ja) 2012-06-29 2016-01-20 株式会社Sumco エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ
US10233562B2 (en) * 2013-04-24 2019-03-19 Sumco Techxiv Corporation Method for producing single crystal, and method for producing silicon wafer
JP6372709B2 (ja) * 2016-04-20 2018-08-15 信越半導体株式会社 エピタキシャルウェーハの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH097961A (ja) * 1995-06-22 1997-01-10 Motorola Inc 高ドープｎ＋基板およびその製造方法
EP1801863A1 (en) * 2004-08-31 2007-06-27 SUMCO Corporation Silicon epitaxial wafer and method for manufacturing the same
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223641A (ja) 1996-12-03 1998-08-21 Sumitomo Sitix Corp 半導体シリコンエピタキシャルウェーハ及び半導体デバイスの製造方法
JP3482982B2 (ja) * 1996-12-12 2004-01-06 三菱住友シリコン株式会社 Ｅｇ層付きエピタキシャルウェーハの製造方法
JP2000031153A (ja) 1998-07-13 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｉウエーハ及びその製造方法
JP4442955B2 (ja) * 1999-07-28 2010-03-31 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
EP1143047B1 (en) 1999-09-29 2015-11-04 Shin-Etsu Handotai Co., Ltd. Method of manufacturing silicon wafer
JP4070949B2 (ja) * 1999-09-29 2008-04-02 三益半導体工業株式会社 ウェーハ、エピタキシャルウェーハ及びそれらの製造方法
JP2003188107A (ja) * 2001-12-19 2003-07-04 Shin Etsu Handotai Co Ltd 半導体エピタキシャルウエーハの製造方法および半導体エピタキシャルウエーハ
JP4516096B2 (ja) * 2007-05-31 2010-08-04 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 シリコン単結晶の製造方法
JP5509581B2 (ja) * 2008-11-27 2014-06-04 信越半導体株式会社 半導体ウェーハの評価方法
JP5246065B2 (ja) * 2009-06-29 2013-07-24 株式会社Ｓｕｍｃｏ エピタキシャルシリコンウェーハとその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH097961A (ja) * 1995-06-22 1997-01-10 Motorola Inc 高ドープｎ＋基板およびその製造方法
EP1801863A1 (en) * 2004-08-31 2007-06-27 SUMCO Corporation Silicon epitaxial wafer and method for manufacturing the same
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates

Also Published As

Publication number Publication date
JP5609025B2 (ja) 2014-10-22
JP2011009614A (ja) 2011-01-13
US20120112190A1 (en) 2012-05-10
US8659020B2 (en) 2014-02-25
DE112010002747T5 (de) 2013-09-26
WO2011001770A1 (ja) 2011-01-06

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