DE102018108554A1 - Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt - Google Patents

Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt Download PDF

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Publication number
DE102018108554A1
DE102018108554A1 DE102018108554.0A DE102018108554A DE102018108554A1 DE 102018108554 A1 DE102018108554 A1 DE 102018108554A1 DE 102018108554 A DE102018108554 A DE 102018108554A DE 102018108554 A1 DE102018108554 A1 DE 102018108554A1
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Germany
Prior art keywords
memory
odt
rank
rnk1
ranks
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Pending
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DE102018108554.0A
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German (de)
English (en)
Inventor
Young-Hoon SON
Si-Hong Kim
Chang-kyo LEE
Jung-hwan Choi
Kyung-Soo Ha
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020170089692A external-priority patent/KR20180130417A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102018108554A1 publication Critical patent/DE102018108554A1/de
Pending legal-status Critical Current

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148Details of power up or power down circuits, standby circuits or recovery circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069I/O lines read out arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109Control signal input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096Write circuits, e.g. I/O line write drivers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38Impedance-matching networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102018108554.0A 2017-05-29 2018-04-11 Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt Pending DE102018108554A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20170066377 2017-05-29
KR10-2017-0066377 2017-05-29
KR10-2017-0089692 2017-07-14
KR1020170089692A KR20180130417A (ko) 2017-05-29 2017-07-14 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템

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DE102018108554A1 true DE102018108554A1 (de) 2018-11-29

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Country Link
US (4) US10566038B2 (enExample)
JP (1) JP7023791B2 (enExample)
CN (2) CN108932960B (enExample)
DE (1) DE102018108554A1 (enExample)

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JP7023791B2 (ja) 2022-02-22
US20200243123A1 (en) 2020-07-30
US20180342274A1 (en) 2018-11-29
US10916279B2 (en) 2021-02-09
US10692554B2 (en) 2020-06-23
US11475930B2 (en) 2022-10-18
CN112951287A (zh) 2021-06-11
CN108932960A (zh) 2018-12-04
US10566038B2 (en) 2020-02-18
JP2018200739A (ja) 2018-12-20
US20210233575A1 (en) 2021-07-29
US20200135247A1 (en) 2020-04-30
CN112951287B (zh) 2022-02-25
CN108932960B (zh) 2021-06-01

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