DE102018108554A1 - Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt - Google Patents
Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt Download PDFInfo
- Publication number
- DE102018108554A1 DE102018108554A1 DE102018108554.0A DE102018108554A DE102018108554A1 DE 102018108554 A1 DE102018108554 A1 DE 102018108554A1 DE 102018108554 A DE102018108554 A DE 102018108554A DE 102018108554 A1 DE102018108554 A1 DE 102018108554A1
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- Germany
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- memory
- odt
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/38—Impedance-matching networks
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20170066377 | 2017-05-29 | ||
| KR10-2017-0066377 | 2017-05-29 | ||
| KR10-2017-0089692 | 2017-07-14 | ||
| KR1020170089692A KR20180130417A (ko) | 2017-05-29 | 2017-07-14 | 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102018108554A1 true DE102018108554A1 (de) | 2018-11-29 |
Family
ID=64109546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102018108554.0A Pending DE102018108554A1 (de) | 2017-05-29 | 2018-04-11 | Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt |
Country Status (4)
| Country | Link |
|---|---|
| US (4) | US10566038B2 (enExample) |
| JP (1) | JP7023791B2 (enExample) |
| CN (2) | CN108932960B (enExample) |
| DE (1) | DE102018108554A1 (enExample) |
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| US10566038B2 (en) | 2017-05-29 | 2020-02-18 | Samsung Electronics Co., Ltd. | Method of controlling on-die termination and system performing the same |
| KR101970319B1 (ko) * | 2017-09-14 | 2019-08-13 | 주식회사 힘펠 | 전열교환기 |
| US10424356B2 (en) | 2017-11-22 | 2019-09-24 | Micron Technology, Inc. | Methods for on-die memory termination and memory devices and systems employing the same |
| KR102665412B1 (ko) | 2018-03-27 | 2024-05-20 | 삼성전자주식회사 | 멀티-랭크들의 온-다이 터미네이션(odt) 셋팅을 최적화하는 방법 및 메모리 시스템 |
| US10318464B1 (en) * | 2018-06-28 | 2019-06-11 | Montage Technology Co., Ltd. | Memory system and method for accessing memory system |
| US10797700B2 (en) | 2018-12-21 | 2020-10-06 | Samsung Electronics Co., Ltd. | Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device |
| KR20200086137A (ko) * | 2019-01-08 | 2020-07-16 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| CN112817884B (zh) * | 2019-11-15 | 2025-04-04 | 安徽寒武纪信息科技有限公司 | 一种存储器以及包括该存储器的设备 |
| KR102778721B1 (ko) * | 2019-12-05 | 2025-03-11 | 삼성전자주식회사 | 온-다이 터미네이션의 제어 방법 및 이를 수행하는 메모리 시스템 |
| US20200133669A1 (en) * | 2019-12-23 | 2020-04-30 | Intel Corporation | Techniques for dynamic proximity based on-die termination |
| KR102849551B1 (ko) * | 2020-08-18 | 2025-08-22 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
| US11810638B2 (en) * | 2020-09-29 | 2023-11-07 | Samsung Electronics Co., Ltd. | Memory device including multiple memory chips and data signal lines and a method of operating the memory device |
| TWI809541B (zh) | 2021-03-09 | 2023-07-21 | 南韓商三星電子股份有限公司 | 與記憶體控制器進行通訊的記憶體元件的操作方法、以及包括其之電子元件的操作方法 |
| KR20220126833A (ko) | 2021-03-09 | 2022-09-19 | 삼성전자주식회사 | 데이터 클럭의 동기화를 연장하는 메모리 장치의 동작 방법, 및 메모리 장치를 포함하는 전자 장치의 동작 방법 |
| WO2023038790A1 (en) * | 2021-09-07 | 2023-03-16 | Rambus Inc. | Common data strobe among multiple memory devices |
| JP7490790B2 (ja) * | 2022-03-25 | 2024-05-27 | チャンシン メモリー テクノロジーズ インコーポレイテッド | 制御方法、半導体メモリ及び電子機器 |
| KR20250020709A (ko) | 2022-03-25 | 2025-02-11 | 창신 메모리 테크놀로지즈 아이엔씨 | 제어 방법, 반도체 메모리 및 전자 기기 |
| KR20250022229A (ko) * | 2022-03-25 | 2025-02-14 | 창신 메모리 테크놀로지즈 아이엔씨 | 제어 방법, 반도체 메모리 및 전자 기기 |
| US12142314B2 (en) * | 2022-04-20 | 2024-11-12 | Samsung Electronics Co., Ltd. | Semiconductor die for controlling on-die-termination of another semiconductor die, and semiconductor devices including the same |
| US12333169B2 (en) | 2022-04-25 | 2025-06-17 | Samsung Electronics Co., Ltd. | Memory system for optimizing on-die termination settings of multi-ranks, method of operation of memory system, and memory controller |
| KR20240039924A (ko) | 2022-09-20 | 2024-03-27 | 삼성전자주식회사 | 다양한 동작 모드를 가지는 반도체 메모리 장치 및 메모리 모듈 |
| CN118866040B (zh) * | 2023-04-14 | 2025-10-03 | 长鑫存储技术有限公司 | 一种命令产生电路和存储器 |
| US20250245145A1 (en) * | 2024-01-29 | 2025-07-31 | Western Digital Technologies, Inc. | Non-target on-die termination |
| CN118969051A (zh) * | 2024-10-12 | 2024-11-15 | 博越微电子(江苏)有限公司 | 一种lpddr5x的全速自测方法及系统 |
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| KR20170089692A (ko) | 2016-01-27 | 2017-08-04 | 주식회사 스맥 | 전동식 건물 비상 탈출 장치 |
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2018
- 2018-03-12 US US15/918,526 patent/US10566038B2/en active Active
- 2018-04-11 DE DE102018108554.0A patent/DE102018108554A1/de active Pending
- 2018-05-28 CN CN201810522583.2A patent/CN108932960B/zh active Active
- 2018-05-28 CN CN202110219921.7A patent/CN112951287B/zh active Active
- 2018-05-29 JP JP2018102557A patent/JP7023791B2/ja active Active
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2019
- 2019-12-19 US US16/721,131 patent/US10692554B2/en active Active
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2020
- 2020-04-14 US US16/848,364 patent/US10916279B2/en active Active
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2021
- 2021-01-05 US US17/141,357 patent/US11475930B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170066377A (ko) | 2014-09-30 | 2017-06-14 | 샌디스크 테크놀로지스 엘엘씨 | 빗살 형상의 소스 전극을 갖는 3차원 메모리 디바이스 및 그 제조 방법 |
| KR20170089692A (ko) | 2016-01-27 | 2017-08-04 | 주식회사 스맥 | 전동식 건물 비상 탈출 장치 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7023791B2 (ja) | 2022-02-22 |
| US20200243123A1 (en) | 2020-07-30 |
| US20180342274A1 (en) | 2018-11-29 |
| US10916279B2 (en) | 2021-02-09 |
| US10692554B2 (en) | 2020-06-23 |
| US11475930B2 (en) | 2022-10-18 |
| CN112951287A (zh) | 2021-06-11 |
| CN108932960A (zh) | 2018-12-04 |
| US10566038B2 (en) | 2020-02-18 |
| JP2018200739A (ja) | 2018-12-20 |
| US20210233575A1 (en) | 2021-07-29 |
| US20200135247A1 (en) | 2020-04-30 |
| CN112951287B (zh) | 2022-02-25 |
| CN108932960B (zh) | 2021-06-01 |
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