DE102018010677B4 - Verfahren zum Betreiben eines dynamischen Low-Power-Double-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM) - Google Patents

Verfahren zum Betreiben eines dynamischen Low-Power-Double-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM)

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Publication number
DE102018010677B4
DE102018010677B4 DE102018010677.3A DE102018010677A DE102018010677B4 DE 102018010677 B4 DE102018010677 B4 DE 102018010677B4 DE 102018010677 A DE102018010677 A DE 102018010677A DE 102018010677 B4 DE102018010677 B4 DE 102018010677B4
Authority
DE
Germany
Prior art keywords
memory
rnk1
memory rank
rank
odt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102018010677.3A
Other languages
German (de)
English (en)
Inventor
Young-Hoon SON
Si-Hong Kim
Chang-kyo LEE
Jung-hwan Choi
Kyung-Soo Ha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170089692A external-priority patent/KR20180130417A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE102018010677B4 publication Critical patent/DE102018010677B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102018010677.3A 2017-05-29 2018-04-11 Verfahren zum Betreiben eines dynamischen Low-Power-Double-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM) Active DE102018010677B4 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20170066377 2017-05-29
KR10-2017-0066377 2017-05-29
KR10-2017-0089692 2017-07-14
KR1020170089692A KR20180130417A (ko) 2017-05-29 2017-07-14 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템

Publications (1)

Publication Number Publication Date
DE102018010677B4 true DE102018010677B4 (de) 2026-03-19

Family

ID=64109546

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102018010677.3A Active DE102018010677B4 (de) 2017-05-29 2018-04-11 Verfahren zum Betreiben eines dynamischen Low-Power-Double-Rate-5-Direktzugriffsspeichers (LPDDR5-DRAM)
DE102018108554.0A Pending DE102018108554A1 (de) 2017-05-29 2018-04-11 Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE102018108554.0A Pending DE102018108554A1 (de) 2017-05-29 2018-04-11 Verfahren zum Steuern einer On-Die-Terminierung und System, welches dasselbe durchführt

Country Status (4)

Country Link
US (4) US10566038B2 (https=)
JP (1) JP7023791B2 (https=)
CN (2) CN112951287B (https=)
DE (2) DE102018010677B4 (https=)

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US12142314B2 (en) * 2022-04-20 2024-11-12 Samsung Electronics Co., Ltd. Semiconductor die for controlling on-die-termination of another semiconductor die, and semiconductor devices including the same
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Also Published As

Publication number Publication date
DE102018108554A1 (de) 2018-11-29
US20200135247A1 (en) 2020-04-30
CN108932960A (zh) 2018-12-04
US10692554B2 (en) 2020-06-23
CN112951287B (zh) 2022-02-25
JP7023791B2 (ja) 2022-02-22
US20200243123A1 (en) 2020-07-30
US20180342274A1 (en) 2018-11-29
US10916279B2 (en) 2021-02-09
US11475930B2 (en) 2022-10-18
US20210233575A1 (en) 2021-07-29
CN112951287A (zh) 2021-06-11
CN108932960B (zh) 2021-06-01
US10566038B2 (en) 2020-02-18
JP2018200739A (ja) 2018-12-20

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