DE102005037869B4 - Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung - Google Patents

Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung Download PDF

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Publication number
DE102005037869B4
DE102005037869B4 DE102005037869A DE102005037869A DE102005037869B4 DE 102005037869 B4 DE102005037869 B4 DE 102005037869B4 DE 102005037869 A DE102005037869 A DE 102005037869A DE 102005037869 A DE102005037869 A DE 102005037869A DE 102005037869 B4 DE102005037869 B4 DE 102005037869B4
Authority
DE
Germany
Prior art keywords
layer
package according
hermetically sealing
substrate
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102005037869A
Other languages
German (de)
English (en)
Other versions
DE102005037869A1 (de
Inventor
Michael Kaspar
Herbert Schwarzbauer
Karl Weidner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE102005037869A priority Critical patent/DE102005037869B4/de
Priority to JP2008525534A priority patent/JP5174664B2/ja
Priority to US11/990,263 priority patent/US7897881B2/en
Priority to PCT/EP2006/064787 priority patent/WO2007017404A2/de
Publication of DE102005037869A1 publication Critical patent/DE102005037869A1/de
Application granted granted Critical
Publication of DE102005037869B4 publication Critical patent/DE102005037869B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1311—Foil encapsulation, e.g. of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1322—Encapsulation comprising more than one layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Laminated Bodies (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE102005037869A 2005-08-10 2005-08-10 Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung Expired - Fee Related DE102005037869B4 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE102005037869A DE102005037869B4 (de) 2005-08-10 2005-08-10 Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung
JP2008525534A JP5174664B2 (ja) 2005-08-10 2006-07-28 密閉用のパッケージ及びパッケージの製造方法
US11/990,263 US7897881B2 (en) 2005-08-10 2006-07-28 Arrangement for hermetically sealing components, and method for the production thereof
PCT/EP2006/064787 WO2007017404A2 (de) 2005-08-10 2006-07-28 Anordnung zur hermetischen abdichtung von bauelementen und verfahren zu deren herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005037869A DE102005037869B4 (de) 2005-08-10 2005-08-10 Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung

Publications (2)

Publication Number Publication Date
DE102005037869A1 DE102005037869A1 (de) 2007-02-15
DE102005037869B4 true DE102005037869B4 (de) 2007-05-31

Family

ID=37681045

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102005037869A Expired - Fee Related DE102005037869B4 (de) 2005-08-10 2005-08-10 Anordnung zur hermetischen Abdichtung von Bauelementen und Verfahren zu deren Herstellung

Country Status (4)

Country Link
US (1) US7897881B2 (https=)
JP (1) JP5174664B2 (https=)
DE (1) DE102005037869B4 (https=)
WO (1) WO2007017404A2 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007036045A1 (de) * 2007-08-01 2009-02-05 Siemens Ag Elektronischer Baustein mit zumindest einem Bauelement, insbesondere einem Halbleiterbauelement, und Verfahren zu dessen Herstellung
US20090091005A1 (en) * 2007-10-09 2009-04-09 Huang Chung-Er Shielding structure for semiconductors and manufacturing method therefor
DE102008031231B4 (de) * 2008-07-02 2012-12-27 Siemens Aktiengesellschaft Herstellungsverfahren für planare elektronsche Leistungselektronik-Module für Hochtemperatur-Anwendungen und entsprechendes Leistungselektronik-Modul
EP2161974A1 (de) * 2008-09-09 2010-03-10 Hegutechnik v. Gutwald KG Bifunktionale EMV Beschichtung
US20110270028A1 (en) * 2010-04-30 2011-11-03 Allergan, Inc. Biocompatible and biostable implantable medical device
US20120188727A1 (en) * 2011-01-24 2012-07-26 ADL Engineering Inc. EMI Shielding in a Package Module
US9064883B2 (en) * 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
DE102011112476A1 (de) * 2011-09-05 2013-03-07 Epcos Ag Bauelement und Verfahren zum Herstellen eines Bauelements
CN102548239A (zh) * 2012-01-09 2012-07-04 华为终端有限公司 一种电路板的制作方法、电路板和电子设备
US9146207B2 (en) 2012-01-10 2015-09-29 Hzo, Inc. Methods, apparatuses and systems for sensing exposure of electronic devices to moisture
WO2013106253A1 (en) 2012-01-10 2013-07-18 Hzo Inc. Methods, apparatuses and systems for monitoring for exposure of electronic devices to moisture and reacting to exposure of electronic devices to moisture
US10449568B2 (en) 2013-01-08 2019-10-22 Hzo, Inc. Masking substrates for application of protective coatings
US9894776B2 (en) 2013-01-08 2018-02-13 Hzo, Inc. System for refurbishing or remanufacturing an electronic device
CN104994965A (zh) 2013-01-08 2015-10-21 Hzo股份有限公司 用于施涂保护性涂层的掩蔽基底
CN103594434B (zh) * 2013-10-23 2017-12-29 广东明路电力电子有限公司 带复合散热层的功率部件
EP3009774B1 (en) * 2014-10-14 2022-03-02 Carel Industries S.p.A. Control device for refrigeration and conditioning systems
DE102014115565B3 (de) 2014-10-27 2015-10-22 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung einer Schalteinrichtung mit einer feuchtigkeitsdichten und elektrisch isolierenden Abdeckung und zur Herstellung einer Anordnung hiermit
JP2019012722A (ja) * 2017-06-29 2019-01-24 株式会社ケーヒン 制御回路装置
US11034068B2 (en) * 2018-04-30 2021-06-15 Raytheon Company Encapsulating electronics in high-performance thermoplastics

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492194B1 (en) * 1999-10-15 2002-12-10 Thomson-Csf Method for the packaging of electronic components

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JPS6218739A (ja) * 1985-07-18 1987-01-27 Sumitomo Electric Ind Ltd 混成集積回路
US5051275A (en) * 1989-11-09 1991-09-24 At&T Bell Laboratories Silicone resin electronic device encapsulant
US5439849A (en) * 1994-02-02 1995-08-08 At&T Corp. Encapsulation techniques which include forming a thin glass layer onto a polymer layer
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
US5811050A (en) * 1994-06-06 1998-09-22 Gabower; John F. Electromagnetic interference shield for electronic devices
JPH1050763A (ja) * 1996-07-30 1998-02-20 Matsushita Electric Ind Co Ltd 電子部品実装方法と電子部品実装基板
TW517368B (en) * 2002-01-22 2003-01-11 Via Tech Inc Manufacturing method of the passivation metal on the surface of integrated circuit
JP2003243704A (ja) * 2002-02-07 2003-08-29 Lumileds Lighting Us Llc 発光半導体デバイス及び方法
US6781231B2 (en) * 2002-09-10 2004-08-24 Knowles Electronics Llc Microelectromechanical system package with environmental and interference shield
JP2004193517A (ja) * 2002-12-13 2004-07-08 Seiko Epson Corp 半導体チップ、半導体チップの製造方法、半導体実装基板、電子デバイスおよび電子機器
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Patent Citations (1)

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Also Published As

Publication number Publication date
US7897881B2 (en) 2011-03-01
WO2007017404A2 (de) 2007-02-15
WO2007017404A3 (de) 2008-08-21
DE102005037869A1 (de) 2007-02-15
US20100089633A1 (en) 2010-04-15
JP5174664B2 (ja) 2013-04-03
JP2009505386A (ja) 2009-02-05

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee