DE102004050037A1 - Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren - Google Patents

Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren Download PDF

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Publication number
DE102004050037A1
DE102004050037A1 DE102004050037A DE102004050037A DE102004050037A1 DE 102004050037 A1 DE102004050037 A1 DE 102004050037A1 DE 102004050037 A DE102004050037 A DE 102004050037A DE 102004050037 A DE102004050037 A DE 102004050037A DE 102004050037 A1 DE102004050037 A1 DE 102004050037A1
Authority
DE
Germany
Prior art keywords
row
mode
address signal
operating mode
column decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE102004050037A
Other languages
English (en)
Other versions
DE102004050037B4 (de
Inventor
Young-Gu Kang
Jong-Hyun Choi
Woo-Seop Jeong
Ki-Ho Jang
Jung-Yong Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020030070311A external-priority patent/KR100560773B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102004050037A1 publication Critical patent/DE102004050037A1/de
Application granted granted Critical
Publication of DE102004050037B4 publication Critical patent/DE102004050037B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Die Erfindung bezieht sich auf ein Speicherbauelement mit einem Speicherzellenfeld (140), einem Zeilendecoder (110), welcher eine Zeile des Speicherzellenfeldes (140) gemäß einem Mehrbitadressensignal auswählt, und einem Spaltendecoder (120), welcher eine Spalte des Speicherzellenfeldes (140) gemäß dem Mehrbitadressensignal auswählt, auf ein zugehöriges Speichersystem sowie auf ein zugehöriges Verfahren zum Setzen eines Betriebsmodus. DOLLAR A Erfindungsgemäß ist eine Modussteuerschaltung vorgesehen, welche wenigstens ein Bit des Mehrbitadressensignals empfängt, das zur Auswahl der Zeile und/oder der Spalte durch den Zeilendecoder (110) und/oder Spaltendecoder (120) benutzt wird, und einen Betriebsmodus des Speicherbauelements (230) gemäß dem wenigstens einen Bit setzt, wobei der Betriebsmodus einen Bündellängenmodus und/oder einen DLL-Rücksetzmodus und/oder einen Testmodus und/oder einen CAS-Latenzmodus und/oder einen Bündeltypmodus umfasst. DOLLAR A Verwendung z. B. für Halbleiterspeicherbausteine.
DE102004050037.1A 2003-10-09 2004-10-07 Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren Expired - Fee Related DE102004050037B4 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR2003-70311 2003-10-09
KR1020030070311A KR100560773B1 (ko) 2003-10-09 2003-10-09 동작 모드의 재설정없이 버스트 길이를 제어할 수 있는반도체 메모리 장치 및 그것을 포함하는 메모리 시스템
US10/951,881 US7042800B2 (en) 2003-10-09 2004-09-29 Method and memory system in which operating mode is set using address signal
US10/951,881 2004-09-29

Publications (2)

Publication Number Publication Date
DE102004050037A1 true DE102004050037A1 (de) 2005-05-12
DE102004050037B4 DE102004050037B4 (de) 2015-01-08

Family

ID=34437023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004050037.1A Expired - Fee Related DE102004050037B4 (de) 2003-10-09 2004-10-07 Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren

Country Status (4)

Country Link
JP (1) JP2005116167A (de)
CN (1) CN1652248B (de)
DE (1) DE102004050037B4 (de)
TW (1) TWI258143B (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724626B1 (ko) 2005-08-29 2007-06-04 주식회사 하이닉스반도체 테스트 모드 제어 회로
KR100656464B1 (ko) 2005-12-28 2006-12-11 주식회사 하이닉스반도체 반도체 메모리의 출력 인에이블 신호 생성장치 및 방법
US7982511B2 (en) 2006-02-09 2011-07-19 Hynix Semiconductor Inc. DLL circuit and method of controlling the same
KR100695436B1 (ko) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자 및그의 동작 모드 제어방법
KR100799132B1 (ko) 2006-06-29 2008-01-29 주식회사 하이닉스반도체 초기값변경이 가능한 모드레지스터셋회로.
CN101202115B (zh) * 2006-12-15 2010-05-19 上海华虹Nec电子有限公司 内置非挥发性存储器芯片的测试模式实现方法
JP4984872B2 (ja) * 2006-12-15 2012-07-25 富士通セミコンダクター株式会社 半導体メモリ、半導体メモリの動作方法、メモリコントローラおよびシステム
KR100892670B1 (ko) 2007-09-05 2009-04-15 주식회사 하이닉스반도체 반도체 메모리 장치의 프리차지 제어 회로
JP5471406B2 (ja) * 2009-12-18 2014-04-16 日本電気株式会社 半導体検証装置および方法
CN103336751B (zh) * 2013-07-10 2015-12-30 广西科技大学 寻址功能与存储单元一体化存储控制器
CN104698917B (zh) * 2013-12-10 2018-12-28 爱思开海力士有限公司 半导体装置的操作模式设定电路和利用其的数据处理系统
KR102164019B1 (ko) * 2014-01-27 2020-10-12 에스케이하이닉스 주식회사 버스트 랭스 제어 장치 및 이를 포함하는 반도체 장치
US9471254B2 (en) * 2014-04-16 2016-10-18 Sandisk Technologies Llc Storage module and method for adaptive burst mode
WO2020197925A1 (en) * 2019-03-26 2020-10-01 Rambus Inc. Multiple precision memory system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998013828A1 (fr) * 1996-09-26 1998-04-02 Mitsubishi Denki Kabushiki Kaisha Memoire a semi-conducteur du type synchrone
JPH10208468A (ja) * 1997-01-28 1998-08-07 Hitachi Ltd 半導体記憶装置並びに同期型半導体記憶装置
DE19915081C2 (de) * 1999-04-01 2001-10-18 Infineon Technologies Ag Integrierter Speicher, dessen Speicherzellen mit Plattenleitungen verbunden sind
US6275437B1 (en) * 2000-06-30 2001-08-14 Samsung Electronics Co., Ltd. Refresh-type memory with zero write recovery time and no maximum cycle time
JP4011833B2 (ja) * 2000-06-30 2007-11-21 株式会社東芝 半導体メモリ

Also Published As

Publication number Publication date
TWI258143B (en) 2006-07-11
TW200519943A (en) 2005-06-16
DE102004050037B4 (de) 2015-01-08
CN1652248B (zh) 2011-06-01
JP2005116167A (ja) 2005-04-28
CN1652248A (zh) 2005-08-10

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