ATE395702T1 - Programmierbares chipauswahlsignal - Google Patents

Programmierbares chipauswahlsignal

Info

Publication number
ATE395702T1
ATE395702T1 AT04756865T AT04756865T ATE395702T1 AT E395702 T1 ATE395702 T1 AT E395702T1 AT 04756865 T AT04756865 T AT 04756865T AT 04756865 T AT04756865 T AT 04756865T AT E395702 T1 ATE395702 T1 AT E395702T1
Authority
AT
Austria
Prior art keywords
chip select
generate
address decoder
memory device
encoded
Prior art date
Application number
AT04756865T
Other languages
English (en)
Inventor
Peter Munguia
Eric Wang
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE395702T1 publication Critical patent/ATE395702T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Circuits Of Receivers In General (AREA)
  • Dram (AREA)
AT04756865T 2003-07-22 2004-07-08 Programmierbares chipauswahlsignal ATE395702T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/625,285 US20050021922A1 (en) 2003-07-22 2003-07-22 Programmable chip select

Publications (1)

Publication Number Publication Date
ATE395702T1 true ATE395702T1 (de) 2008-05-15

Family

ID=34080175

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04756865T ATE395702T1 (de) 2003-07-22 2004-07-08 Programmierbares chipauswahlsignal

Country Status (9)

Country Link
US (1) US20050021922A1 (de)
EP (1) EP1647027B1 (de)
JP (1) JP2006528386A (de)
KR (1) KR100869920B1 (de)
CN (1) CN1826657A (de)
AT (1) ATE395702T1 (de)
DE (1) DE602004013784D1 (de)
TW (1) TWI254249B (de)
WO (1) WO2005010890A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100468378C (zh) * 2005-12-17 2009-03-11 鸿富锦精密工业（深圳）有限公司 Spi设备通信电路
KR100762206B1 (ko) * 2006-06-08 2007-10-01 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 칩 선택 신호 발생방법
DE102007051521A1 (de) * 2007-10-19 2009-04-23 Seereal Technologies S.A. Dynamische Wellenformereinheit
US9104557B2 (en) * 2008-08-01 2015-08-11 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Encoded chip select for supporting more memory ranks
US8239629B2 (en) * 2009-03-31 2012-08-07 Micron Technology, Inc. Hierarchical memory architecture to connect mass storage devices
CN102087636A (zh) * 2009-12-08 2011-06-08 上海华虹集成电路有限责任公司 多通道Nandflash控制器
KR20110119087A (ko) 2010-04-26 2011-11-02 삼성전자주식회사 스택형 반도체 장치
US10074417B2 (en) 2014-11-20 2018-09-11 Rambus Inc. Memory systems and methods for improved power management
US9710128B2 (en) * 2015-03-17 2017-07-18 Google Inc. Dynamic icons for gesture discoverability

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5617559A (en) * 1994-08-31 1997-04-01 Motorola Inc. Modular chip select control circuit and method for performing pipelined memory accesses
US5511182A (en) * 1994-08-31 1996-04-23 Motorola, Inc. Programmable pin configuration logic circuit for providing a chip select signal and related method
EP0733976A1 (de) * 1995-03-23 1996-09-25 Canon Kabushiki Kaisha Chipauswahlsignalgenerator
US5802541A (en) * 1996-02-28 1998-09-01 Motorola, Inc. Method and apparatus in a data processing system for using chip selects to perform a memory management function
US6744925B2 (en) * 1996-03-19 2004-06-01 Mitsubishi Denki Kabushiki Kaisha Encoding apparatus, decoding apparatus, encoding method, and decoding method
US6199151B1 (en) * 1998-06-05 2001-03-06 Intel Corporation Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle
US20010047473A1 (en) * 2000-02-03 2001-11-29 Realtime Data, Llc Systems and methods for computer initialization
JP3778087B2 (ja) * 2002-01-18 2006-05-24 富士ゼロックス株式会社 データ符号化装置及びデータ復号装置

Also Published As

Publication number Publication date
KR100869920B1 (ko) 2008-11-24
CN1826657A (zh) 2006-08-30
EP1647027B1 (de) 2008-05-14
KR20060030517A (ko) 2006-04-10
JP2006528386A (ja) 2006-12-14
DE602004013784D1 (de) 2008-06-26
EP1647027A1 (de) 2006-04-19
TW200521847A (en) 2005-07-01
TWI254249B (en) 2006-05-01
WO2005010890A1 (en) 2005-02-03
US20050021922A1 (en) 2005-01-27

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Legal Events

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